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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
H A Dsetup-sh7264.c233 DEFINE_RES_MEM(0xfffe8000, 0x100),
257 DEFINE_RES_MEM(0xfffe8800, 0x100),
281 DEFINE_RES_MEM(0xfffe9000, 0x100),
305 DEFINE_RES_MEM(0xfffe9800, 0x100),
329 DEFINE_RES_MEM(0xfffea000, 0x100),
353 DEFINE_RES_MEM(0xfffea800, 0x100),
377 DEFINE_RES_MEM(0xfffeb000, 0x100),
401 DEFINE_RES_MEM(0xfffeb800, 0x100),
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
H A Deseries.c176 .atag_offset = 0x100,
228 .atag_offset = 0x100,
353 .atag_offset = 0x100,
550 .atag_offset = 0x100,
750 .atag_offset = 0x100,
858 tmp |= 0x100; in e800_tg_change()
860 tmp &= ~0x100; in e800_tg_change()
968 .atag_offset = 0x100,
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2a/
H A Dsetup-sh7269.c255 DEFINE_RES_MEM(0xe8007000, 0x100),
279 DEFINE_RES_MEM(0xe8007800, 0x100),
303 DEFINE_RES_MEM(0xe8008000, 0x100),
327 DEFINE_RES_MEM(0xe8008800, 0x100),
351 DEFINE_RES_MEM(0xe8009000, 0x100),
375 DEFINE_RES_MEM(0xe8009800, 0x100),
399 DEFINE_RES_MEM(0xe800a000, 0x100),
423 DEFINE_RES_MEM(0xe800a800, 0x100),
H A Dsetup-sh7264.c233 DEFINE_RES_MEM(0xfffe8000, 0x100),
257 DEFINE_RES_MEM(0xfffe8800, 0x100),
281 DEFINE_RES_MEM(0xfffe9000, 0x100),
305 DEFINE_RES_MEM(0xfffe9800, 0x100),
329 DEFINE_RES_MEM(0xfffea000, 0x100),
353 DEFINE_RES_MEM(0xfffea800, 0x100),
377 DEFINE_RES_MEM(0xfffeb000, 0x100),
401 DEFINE_RES_MEM(0xfffeb800, 0x100),
/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dwm8978.c631 snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0); in wm8978_set_dai_sysclk()
653 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, in wm8978_set_dai_fmt()
698 iface |= 0x100; in wm8978_set_dai_fmt()
727 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ? in wm8978_hw_params()
830 0x100, 0x100); in wm8978_hw_params()
833 snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0); in wm8978_hw_params()
989 snd_soc_component_update_bits(component, update_reg[i], 0x100, 0x100); in wm8978_probe()
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dwm8978.c631 snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0); in wm8978_set_dai_sysclk()
653 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, in wm8978_set_dai_fmt()
698 iface |= 0x100; in wm8978_set_dai_fmt()
727 enum wm8978_sysclk_src current_clk_id = (clking & 0x100) ? in wm8978_hw_params()
830 0x100, 0x100); in wm8978_hw_params()
833 snd_soc_component_update_bits(component, WM8978_CLOCKING, 0x100, 0); in wm8978_hw_params()
989 snd_soc_component_update_bits(component, update_reg[i], 0x100, 0x100); in wm8978_probe()
/third_party/lame/misc/
H A Dabx.c600 c = sel () + 0x100; in testing()
610 case 0x100+'0' : in testing()
679 case 'D'+0x100: in testing()
686 case 'd'+0x100: in testing()
714 case 0x100+'1' : in testing()
715 case 0x100+'2' : in testing()
716 case 0x100+'3' : in testing()
717 case 0x100+'4' : in testing()
718 case 0x100+'5' : in testing()
719 case 0x100 in testing()
[all...]
/device/soc/rockchip/common/vendor/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h369 .end = (gp_addr) + 0x100, \
383 .end = (gp_addr) + 0x100, \
395 .end = (gp_mmu_addr) + 0x100, \
435 .end = (pp_mmu_addr) + 0x100, \
449 .end = (mmu_addr) + 0x100, \
463 .end = (pmu_addr) + 0x100, \
471 .end = (dma_addr) + 0x100, \
479 .end = (dlbu_addr) + 0x100, \
487 .end = (bcast_addr) + 0x100, \
509 .end = (pp_mmu_bcast_addr) + 0x100, \
[all...]
/device/soc/rockchip/common/kernel/drivers/gpu/arm/mali400/mali/include/linux/mali/
H A Dmali_utgard.h290 .end = gp_addr + 0x100, \
304 .end = gp_addr + 0x100, \
316 .end = gp_mmu_addr + 0x100, \
356 .end = pp_mmu_addr + 0x100, \
370 .end = mmu_addr + 0x100, \
384 .end = pmu_addr + 0x100, \
392 .end = dma_addr + 0x100, \
400 .end = dlbu_addr + 0x100, \
408 .end = bcast_addr + 0x100, \
430 .end = pp_mmu_bcast_addr + 0x100, \
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h139 #define UVD_CGC_GATE__MPRD_MASK 0x100
179 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
283 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
351 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
397 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
545 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
587 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
701 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
725 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
[all...]
H A Duvd_3_1_sh_mask.h139 #define UVD_CGC_GATE__MPRD_MASK 0x100
179 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
283 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
347 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
393 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
541 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
581 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
695 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
719 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
[all...]
/kernel/linux/linux-5.10/drivers/media/platform/sti/hva/
H A Dhva-h264.c785 td->addr_spatial_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
788 td->addr_temporal_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
791 td->addr_temporal_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
794 td->addr_spatial_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
799 td->addr_brc_in_out_parameter = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
802 td->addr_slice_header = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
803 td->addr_external_sw = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
806 td->addr_local_rec_buffer = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
809 td->addr_lctx = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
812 td->addr_cabac_context_buffer = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
[all...]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
470 /* 1. Page1(0x100) */
471 #define bBBResetB 0x100 /* Useless now? */
475 #define bCRC32Debug 0x100
503 #define bTxHTMode 0x100
577 #define bRFSI_ANTSW 0x100
650 #define bAD11PowerUpAtRx 0x100
671 #define bAntNonHT 0x100
[all...]
/kernel/linux/linux-5.10/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h13 #define rPMAC_Reset 0x100
228 #define bBBResetB 0x100
232 #define bCRC32Debug 0x100
260 #define bTxHTMode 0x100
326 #define bRFSI_ANTSW 0x100
392 #define bAD11PowerUpAtRx 0x100
417 #define bAntNonHT 0x100
688 #define bHTDetect 0x100
765 #define bAdvUpdCFO 0x100
810 #define bRTL8256RegModeCtrl1 0x100
[all...]
/kernel/linux/linux-5.10/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h37 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
45 * 1. Page1(0x100)
47 #define rPMAC_Reset 0x100
384 * 1. Page1(0x100)
386 #define bBBResetB 0x100 /* Useless now? */
390 #define bCRC32Debug 0x100
418 #define bTxHTMode 0x100
484 #define bRFSI_ANTSW 0x100
554 #define bAD11PowerUpAtRx 0x100
575 #define bAntNonHT 0x100
[all...]
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_global_conf_masks.h43 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_PRST_RST_IND_MASK 0x100
133 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100
249 #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100
331 #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100
529 #define PSOC_GLOBAL_CONF_ARC_LBU_AXI_SPLIT_CTRL2_ARCACHE_OVRD_EN_MASK 0x100
663 #define PSOC_GLOBAL_CONF_BTL_IMG_PRST_RUN_PCIE_IMAGE_MASK 0x100
695 #define PSOC_GLOBAL_CONF_RST_SRC_ECC_DERR_RST_IND_MASK 0x100
809 #define PSOC_GLOBAL_CONF_ASIF_MSTR_ERROR_RX_TIMEOUT_MASK 0x100
837 #define PSOC_GLOBAL_CONF_ASIF_MSTR_INTR_MASK_MASK_RX_TIMEOUT_MASK 0x100
1355 #define PSOC_GLOBAL_CONF_AXI_DRAIN_CTRL_DRAIN_HBW_MASK 0x100
[all...]
/kernel/linux/linux-6.6/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h12 #define rPMAC_Reset 0x100
186 #define bBBResetB 0x100
190 #define bCRC32Debug 0x100
218 #define bTxHTMode 0x100
283 #define bRFSI_ANTSW 0x100
348 #define bAD11PowerUpAtRx 0x100
373 #define bAntNonHT 0x100
644 #define bHTDetect 0x100
721 #define bAdvUpdCFO 0x100
766 #define bRTL8256RegModeCtrl1 0x100
[all...]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/include/
H A DHal8192CPhyReg.h41 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
52 /* 1. Page1(0x100) */
54 #define rPMAC_Reset 0x100
466 /* 1. Page1(0x100) */
467 #define bBBResetB 0x100 /* Useless now? */
471 #define bCRC32Debug 0x100
499 #define bTxHTMode 0x100
572 #define bRFSI_ANTSW 0x100
644 #define bAD11PowerUpAtRx 0x100
665 #define bAntNonHT 0x100
[all...]
/kernel/linux/linux-6.6/drivers/staging/rtl8712/
H A Drtl871x_mp_phy_regdef.h36 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
44 * 1. Page1(0x100)
46 #define rPMAC_Reset 0x100
383 * 1. Page1(0x100)
385 #define bBBResetB 0x100 /* Useless now? */
389 #define bCRC32Debug 0x100
417 #define bTxHTMode 0x100
483 #define bRFSI_ANTSW 0x100
553 #define bAD11PowerUpAtRx 0x100
574 #define bAntNonHT 0x100
[all...]
/kernel/linux/linux-6.6/drivers/media/platform/st/sti/hva/
H A Dhva-h264.c787 td->addr_spatial_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
790 td->addr_temporal_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
793 td->addr_temporal_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
796 td->addr_spatial_context = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
801 td->addr_brc_in_out_parameter = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
804 td->addr_slice_header = ALIGN(paddr, 0x100); in hva_h264_prepare_task()
805 td->addr_external_sw = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
808 td->addr_local_rec_buffer = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
811 td->addr_lctx = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
814 td->addr_cabac_context_buffer = ALIGN(addr_esram, 0x100); in hva_h264_prepare_task()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_3_1_sh_mask.h139 #define UVD_CGC_GATE__MPRD_MASK 0x100
179 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
283 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
347 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
393 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
541 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
581 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
695 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
719 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
[all...]
H A Duvd_4_2_sh_mask.h139 #define UVD_CGC_GATE__MPRD_MASK 0x100
179 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
283 #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
309 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
351 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
397 #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
545 #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
587 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
701 #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
725 #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_irq.h31 #define AMDGPU_MAX_IRQ_SRC_ID 0x100
32 #define AMDGPU_MAX_IRQ_CLIENT_ID 0x100
/kernel/linux/linux-5.10/arch/arm/mach-oxnas/
H A Dplatsmp.c26 #define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson64/
H A Dkernel-entry-init.h44 or t0, 0x100
79 or t0, 0x100

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