18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
48c2ecf20Sopenharmony_ci * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
58c2ecf20Sopenharmony_ci * Copyright (C) 2002 ARM Ltd.
68c2ecf20Sopenharmony_ci * All Rights Reserved
78c2ecf20Sopenharmony_ci */
88c2ecf20Sopenharmony_ci#include <linux/io.h>
98c2ecf20Sopenharmony_ci#include <linux/delay.h>
108c2ecf20Sopenharmony_ci#include <linux/of.h>
118c2ecf20Sopenharmony_ci#include <linux/of_address.h>
128c2ecf20Sopenharmony_ci
138c2ecf20Sopenharmony_ci#include <asm/cacheflush.h>
148c2ecf20Sopenharmony_ci#include <asm/cp15.h>
158c2ecf20Sopenharmony_ci#include <asm/smp_plat.h>
168c2ecf20Sopenharmony_ci#include <asm/smp_scu.h>
178c2ecf20Sopenharmony_ci
188c2ecf20Sopenharmony_ciextern void ox820_secondary_startup(void);
198c2ecf20Sopenharmony_ci
208c2ecf20Sopenharmony_cistatic void __iomem *cpu_ctrl;
218c2ecf20Sopenharmony_cistatic void __iomem *gic_cpu_ctrl;
228c2ecf20Sopenharmony_ci
238c2ecf20Sopenharmony_ci#define HOLDINGPEN_CPU_OFFSET		0xc8
248c2ecf20Sopenharmony_ci#define HOLDINGPEN_LOCATION_OFFSET	0xc4
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci#define GIC_NCPU_OFFSET(cpu)		(0x100 + (cpu)*0x100)
278c2ecf20Sopenharmony_ci#define GIC_CPU_CTRL			0x00
288c2ecf20Sopenharmony_ci#define GIC_CPU_CTRL_ENABLE		1
298c2ecf20Sopenharmony_ci
308c2ecf20Sopenharmony_cistatic int __init ox820_boot_secondary(unsigned int cpu,
318c2ecf20Sopenharmony_ci		struct task_struct *idle)
328c2ecf20Sopenharmony_ci{
338c2ecf20Sopenharmony_ci	/*
348c2ecf20Sopenharmony_ci	 * Write the address of secondary startup into the
358c2ecf20Sopenharmony_ci	 * system-wide flags register. The BootMonitor waits
368c2ecf20Sopenharmony_ci	 * until it receives a soft interrupt, and then the
378c2ecf20Sopenharmony_ci	 * secondary CPU branches to this address.
388c2ecf20Sopenharmony_ci	 */
398c2ecf20Sopenharmony_ci	writel(virt_to_phys(ox820_secondary_startup),
408c2ecf20Sopenharmony_ci			cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci	writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
438c2ecf20Sopenharmony_ci
448c2ecf20Sopenharmony_ci	/*
458c2ecf20Sopenharmony_ci	 * Enable GIC cpu interface in CPU Interface Control Register
468c2ecf20Sopenharmony_ci	 */
478c2ecf20Sopenharmony_ci	writel(GIC_CPU_CTRL_ENABLE,
488c2ecf20Sopenharmony_ci		gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
498c2ecf20Sopenharmony_ci
508c2ecf20Sopenharmony_ci	/*
518c2ecf20Sopenharmony_ci	 * Send the secondary CPU a soft interrupt, thereby causing
528c2ecf20Sopenharmony_ci	 * the boot monitor to read the system wide flags register,
538c2ecf20Sopenharmony_ci	 * and branch to the address found there.
548c2ecf20Sopenharmony_ci	 */
558c2ecf20Sopenharmony_ci	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_ci	return 0;
588c2ecf20Sopenharmony_ci}
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_cistatic void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
618c2ecf20Sopenharmony_ci{
628c2ecf20Sopenharmony_ci	struct device_node *np;
638c2ecf20Sopenharmony_ci	void __iomem *scu_base;
648c2ecf20Sopenharmony_ci
658c2ecf20Sopenharmony_ci	np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
668c2ecf20Sopenharmony_ci	scu_base = of_iomap(np, 0);
678c2ecf20Sopenharmony_ci	of_node_put(np);
688c2ecf20Sopenharmony_ci	if (!scu_base)
698c2ecf20Sopenharmony_ci		return;
708c2ecf20Sopenharmony_ci
718c2ecf20Sopenharmony_ci	/* Remap CPU Interrupt Interface Registers */
728c2ecf20Sopenharmony_ci	np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
738c2ecf20Sopenharmony_ci	gic_cpu_ctrl = of_iomap(np, 1);
748c2ecf20Sopenharmony_ci	of_node_put(np);
758c2ecf20Sopenharmony_ci	if (!gic_cpu_ctrl)
768c2ecf20Sopenharmony_ci		goto unmap_scu;
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_ci	np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
798c2ecf20Sopenharmony_ci	cpu_ctrl = of_iomap(np, 0);
808c2ecf20Sopenharmony_ci	of_node_put(np);
818c2ecf20Sopenharmony_ci	if (!cpu_ctrl)
828c2ecf20Sopenharmony_ci		goto unmap_scu;
838c2ecf20Sopenharmony_ci
848c2ecf20Sopenharmony_ci	scu_enable(scu_base);
858c2ecf20Sopenharmony_ci	flush_cache_all();
868c2ecf20Sopenharmony_ci
878c2ecf20Sopenharmony_ciunmap_scu:
888c2ecf20Sopenharmony_ci	iounmap(scu_base);
898c2ecf20Sopenharmony_ci}
908c2ecf20Sopenharmony_ci
918c2ecf20Sopenharmony_cistatic const struct smp_operations ox820_smp_ops __initconst = {
928c2ecf20Sopenharmony_ci	.smp_prepare_cpus	= ox820_smp_prepare_cpus,
938c2ecf20Sopenharmony_ci	.smp_boot_secondary	= ox820_boot_secondary,
948c2ecf20Sopenharmony_ci};
958c2ecf20Sopenharmony_ci
968c2ecf20Sopenharmony_ciCPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);
97