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/third_party/skia/third_party/externals/icu/source/common/unicode/
H A Duidna.h475 UIDNA_ERROR_PUNYCODE=0x100,
/third_party/rust/crates/rust-openssl/openssl-sys/src/
H A Dx509_vfy.rs114 pub const X509_V_FLAG_EXPLICIT_POLICY: c_ulong = 0x100;
/third_party/spirv-tools/test/opt/
H A Dset_spec_const_default_value_test.cpp80 {"0x100:1024", true, SpecIdToValueStrMap{{256, "1024"}}},
82 {"101:1 102:2 103:3 104:4 200:201 9999:1000 0x100:333", true,
111 {"0x100:100 256:200", false, SpecIdToValueStrMap{}},
207 SpecIdToValueStrMap{{100, "18446744073709551614"}, {101, "0x100"}},
670 {101, {0x100, 0x0}}},
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_1_sh_mask.h33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
179 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
233 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
483 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
553 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
639 #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
[all...]
H A Dsmu_7_1_0_sh_mask.h33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
179 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
231 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
481 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
551 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
637 #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
[all...]
H A Dsmu_7_1_2_sh_mask.h33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
179 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
233 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
357 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
501 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
571 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_2_sh_mask.h33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
179 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
233 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
357 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100
501 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
571 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
[all...]
H A Dsmu_7_1_0_sh_mask.h33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
179 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
231 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
481 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
551 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
637 #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
[all...]
H A Dsmu_7_0_1_sh_mask.h33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
179 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
233 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
483 #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100
553 #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100
639 #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
[all...]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h301 #define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
302 #define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
303 #define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0
304 #define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6
305 #define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2
306 #define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
307 #define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0
/kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h301 #define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
302 #define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
303 #define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0
304 #define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6
305 #define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2
306 #define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
307 #define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0
/kernel/linux/linux-5.10/drivers/video/fbdev/
H A Dneofb.c291 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8) in vgaHWInit()
292 | (((var->yres - 1) & 0x100) >> 7) in vgaHWInit()
293 | ((vsync_start & 0x100) >> 6) in vgaHWInit()
294 | (((var->yres - 1) & 0x100) >> 5) in vgaHWInit()
1847 int CursorOff = 0x100; in neo_init_hw()
1899 CursorOff = 0x100; in neo_init_hw()
1904 CursorOff = 0x100; in neo_init_hw()
H A Datafb.c157 #define VCO_SHORTOFFS 0x100
880 } else if (par->hw.falcon.f_shift & 0x100) { in falcon_encode_fix()
949 par->hw.falcon.st_shift = 0x100; in falcon_decode_var()
959 par->hw.falcon.f_shift = 0x100; /* hicolor, no overlay */ in falcon_decode_var()
1224 if (par->hw.falcon.f_shift & 0x100) { in falcon_decode_var()
1418 else if (hw->f_shift & 0x100) /* hicolor */ in falcon_encode_var()
1424 else if (hw->st_shift == 0x100) in falcon_encode_var()
1476 if (hw->f_shift & 0x100) { in falcon_encode_var()
1566 hw->ste_mode = (hw->f_shift & 0x510) == 0 && hw->st_shift == 0x100; in falcon_get_par()
/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/arm64/freescale/
H A Dimx8mn-pinfunc.h301 #define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
302 #define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
303 #define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0
304 #define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6
305 #define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2
306 #define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
307 #define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0
/kernel/linux/linux-6.6/drivers/video/fbdev/
H A Dneofb.c292 par->CRTC[7] = (((vtotal - 2) & 0x100) >> 8) in vgaHWInit()
293 | (((var->yres - 1) & 0x100) >> 7) in vgaHWInit()
294 | ((vsync_start & 0x100) >> 6) in vgaHWInit()
295 | (((var->yres - 1) & 0x100) >> 5) in vgaHWInit()
1847 int CursorOff = 0x100; in neo_init_hw()
1898 CursorOff = 0x100; in neo_init_hw()
1902 CursorOff = 0x100; in neo_init_hw()
H A Datafb.c155 #define VCO_SHORTOFFS 0x100
868 } else if (par->hw.falcon.f_shift & 0x100) { in falcon_encode_fix()
937 par->hw.falcon.st_shift = 0x100; in falcon_decode_var()
947 par->hw.falcon.f_shift = 0x100; /* hicolor, no overlay */ in falcon_decode_var()
1205 if (par->hw.falcon.f_shift & 0x100) { in falcon_decode_var()
1399 else if (hw->f_shift & 0x100) /* hicolor */ in falcon_encode_var()
1405 else if (hw->st_shift == 0x100) in falcon_encode_var()
1457 if (hw->f_shift & 0x100) { in falcon_encode_var()
1547 hw->ste_mode = (hw->f_shift & 0x510) == 0 && hw->st_shift == 0x100; in falcon_get_par()
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A Dclk-fsd.c28 #define PLL_CON0_PLL_SHARED0 0x100
316 #define PLL_CON0_PERIC_DMACLK_MUX 0x100
675 #define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100
974 #define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100
1146 #define PLL_CON0_CLK_IMEM_ACLK 0x100
1430 #define PLL_CON0_PLL_MFC 0x100
1548 #define PLL_CON0_PLL_CAM_CSI 0x100
/kernel/linux/linux-6.6/drivers/gpu/drm/meson/
H A Dmeson_venc.c370 .video_prog_mode = 0x100,
415 .video_prog_mode = 0x100,
464 .video_prog_mode = 0x100,
513 .video_prog_mode = 0x100,
562 .video_prog_mode = 0x100,
606 .video_prog_mode = 0x100,
654 .video_prog_mode = 0x100,
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/arm64/freescale/
H A Dimx8mn-pinfunc.h301 #define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
302 #define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
303 #define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0
304 #define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6
305 #define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2
306 #define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
307 #define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_emit_nvc0.cpp487 case 0: code[0] |= 0x100 >> ss2a; break; in emitForm_S()
514 case 0: code[0] |= 0x100; break; in emitShortSrc2()
727 addOp |= 0x100; in emitUADD()
729 addOp ^= 0x100; in emitUADD()
750 assert(!(addOp & 0x100)); in emitUADD()
833 code[0] |= (i->subOp & 0x100) >> 3; in emitMADSP()
1328 code[0] |= 0x100; // p mode in emitTEX()
1656 code[0] |= 0x100; in emitVFETCH()
1680 code[0] |= 0x100; in emitEXPORT()
1846 val = 0x100;
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hifb/drv/hi3516cv500/
H A Dhifb_def.h45 #define INTF_REGS_LEN 0x100
665 VDP_GFX_IFMT_STILL_888 = 0x100, /* only use by environment */
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/vo/vo_dev/arch/hi3516cv500/include/
H A Dvou_def.h44 #define INTF_REGS_LEN 0x100
670 VDP_GFX_IFMT_STILL_888 = 0x100, /* only use by environment */
/device/soc/hisilicon/hi3516dv300/sdk_linux/sample/platform/higv/include/
H A Dhi_gv_widget.h221 #define HIGV_STYLE_HILIGHT_CHILD 0x100
503 #define HIGV_MSG_LAN_CHANGE 0x100
/device/soc/rockchip/common/vendor/drivers/mmc/host/
H A Drk_sdmmc.h61 #define SDMMC_CDTHRCTL 0x100
83 * Lower than 2.40a : data register offest is 0x100
85 #define DATA_OFFSET 0x100
/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Dio-domain.c316 .grf_offset = 0x100,
426 .grf_offset = 0x100,

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