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/third_party/backends/backend/
H A Dhs2p.c1122 dev->info.endorser_control = 0x00; in attach()
1124 if ((dev->info.service_mode = get_service_mode (fd)) != 0x00 in attach()
1129 dev->info.service_mode = 0x00; in attach()
1131 if ((dev->info.scan_wait_mode = get_scan_wait_mode (fd)) != 0x00 in attach()
1137 dev->info.scan_wait_mode = 0x00; in attach()
1177 /* dev->sane.backend_capablity_flags = 0x00; */ in attach()
1230 * For IS450 this is set to 0x18 (0001 1000) if IPU installed, else 0x00 in attach()
1231 * For IS420 this is set to 0x3C (0011 1100) if IPU installed, else 0x00 in attach()
1269 /* Marker Recognition is set to 0x00 */ in attach()
1274 * For IS450 this is set to 0x01 when IPU installed; else 0x00 in attach()
[all...]
/third_party/vixl/test/aarch32/traces/
H A Dassembler-cond-rd-rn-operand-rm-shift-rs-bic-a32.h260 0x31, 0x00, 0xc1, 0x71 // bic vc r0 r1 r1 LSR r0
374 0x51, 0x00, 0xc9, 0xa1 // bic ge r0 r9 r1 ASR r0
698 0x36, 0x00, 0xcc, 0xb1 // bic lt r0 r12 r6 LSR r0
2015 0x33, 0x00, 0xcb, 0xc1 // bic gt r0 r11 r3 LSR r0
2699 0x31, 0x00, 0xc9, 0x61 // bic vs r0 r9 r1 LSR r0
2774 0x1a, 0x00, 0xc7, 0x21 // bic cs r0 r7 r10 LSL r0
2957 0x7e, 0x00, 0xc1, 0x71 // bic vc r0 r1 r14 ROR r0
H A Dassembler-cond-rd-rn-operand-rm-shift-rs-bics-a32.h260 0x31, 0x00, 0xd1, 0x71 // bics vc r0 r1 r1 LSR r0
374 0x51, 0x00, 0xd9, 0xa1 // bics ge r0 r9 r1 ASR r0
698 0x36, 0x00, 0xdc, 0xb1 // bics lt r0 r12 r6 LSR r0
2015 0x33, 0x00, 0xdb, 0xc1 // bics gt r0 r11 r3 LSR r0
2699 0x31, 0x00, 0xd9, 0x61 // bics vs r0 r9 r1 LSR r0
2774 0x1a, 0x00, 0xd7, 0x21 // bics cs r0 r7 r10 LSL r0
2957 0x7e, 0x00, 0xd1, 0x71 // bics vc r0 r1 r14 ROR r0
H A Dassembler-cond-rd-rn-operand-rm-shift-rs-orr-a32.h260 0x31, 0x00, 0x81, 0x71 // orr vc r0 r1 r1 LSR r0
374 0x51, 0x00, 0x89, 0xa1 // orr ge r0 r9 r1 ASR r0
698 0x36, 0x00, 0x8c, 0xb1 // orr lt r0 r12 r6 LSR r0
2015 0x33, 0x00, 0x8b, 0xc1 // orr gt r0 r11 r3 LSR r0
2699 0x31, 0x00, 0x89, 0x61 // orr vs r0 r9 r1 LSR r0
2774 0x1a, 0x00, 0x87, 0x21 // orr cs r0 r7 r10 LSL r0
2957 0x7e, 0x00, 0x81, 0x71 // orr vc r0 r1 r14 ROR r0
H A Dassembler-cond-rd-rn-operand-rm-shift-rs-orrs-a32.h260 0x31, 0x00, 0x91, 0x71 // orrs vc r0 r1 r1 LSR r0
374 0x51, 0x00, 0x99, 0xa1 // orrs ge r0 r9 r1 ASR r0
698 0x36, 0x00, 0x9c, 0xb1 // orrs lt r0 r12 r6 LSR r0
2015 0x33, 0x00, 0x9b, 0xc1 // orrs gt r0 r11 r3 LSR r0
2699 0x31, 0x00, 0x99, 0x61 // orrs vs r0 r9 r1 LSR r0
2774 0x1a, 0x00, 0x97, 0x21 // orrs cs r0 r7 r10 LSL r0
2957 0x7e, 0x00, 0x91, 0x71 // orrs vc r0 r1 r14 ROR r0
H A Dassembler-cond-rd-operand-rn-shift-rs-in-it-block-mov-t32.h728 0x88, 0xbf, 0x00, 0x41 // It hi; mov hi r0 r0 ASR r0
761 0xb8, 0xbf, 0x00, 0x41 // It lt; mov lt r0 r0 ASR r0
1091 0x98, 0xbf, 0x00, 0x41 // It ls; mov ls r0 r0 ASR r0
1484 0xa8, 0xbf, 0x00, 0x41 // It ge; mov ge r0 r0 ASR r0
2171 0xd8, 0xbf, 0x00, 0x41 // It le; mov le r0 r0 ASR r0
2273 0x78, 0xbf, 0x00, 0x41 // It vc; mov vc r0 r0 ASR r0
2888 0x28, 0xbf, 0x00, 0x41 // It cs; mov cs r0 r0 ASR r0
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/include/
H A Dhi_comm_hdmi.h773 #define CEC_OPCODE_FEATURE_ABORT 0x00
/device/soc/hisilicon/common/platform/timer/
H A Dtimer_hi35xx.c277 unsigned int maxCnt = ~0x00; /* 32 bit counter */ in TimerHi35xxSetTimeout()
/device/soc/hisilicon/hi3516dv300/sdk_linux/include/
H A Dhi_comm_hdmi.h769 #define CEC_OPCODE_FEATURE_ABORT 0x00
/device/soc/hisilicon/hi3516dv300/sdk_linux/sample/platform/common/
H A Dsample_comm_region.c130 Value_tmp = 0x00; in REGION_MST_LoadBmp()
/device/soc/hisilicon/hi3516dv300/sdk_liteos/include/
H A Dhi_comm_hdmi.h768 #define CEC_OPCODE_FEATURE_ABORT 0x00
/device/soc/hisilicon/hi3861v100/sdk_liteos/third_party/lwip_sack/include/lwip/
H A Dip6_addr.h372 #define IP6_ADDR_INVALID 0x00
H A Dsockets.h528 #define IPTOS_PREC_ROUTINE 0x00
/device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/ispp/
H A Dstream_v20.c273 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x00, SW_FEC_EN); in fec_work_event()
/device/soc/rockchip/common/sdk_linux/drivers/regulator/
H A Dfan53555.c27 #define FAN53555_VSEL0 0x00
/device/soc/rockchip/common/hardware/rga/include/
H A Dim2d.h722 errno_t eok = memset_s(&srcB, sizeof(rga_buffer_t), 0x00, sizeof(rga_buffer_t)); \
/device/soc/rockchip/common/sdk_linux/drivers/nvmem/
H A Drockchip-efuse.c54 #define RK1808_MOD 0x00
/device/soc/rockchip/rk3399/hardware/rga/include/
H A Dim2d.h727 errno_t eok = memset_s(&srcB, sizeof(rga_buffer_t), 0x00, sizeof(rga_buffer_t)); \
/device/soc/rockchip/rk3568/hardware/rga/include/
H A Dim2d.h727 errno_t eok = memset_s(&srcB, sizeof(rga_buffer_t), 0x00, sizeof(rga_buffer_t)); \
/device/soc/rockchip/rk3588/hardware/rga/include/
H A Dim2d.h535 memset(&srcB, 0x00, sizeof(rga_buffer_t)); \
/device/soc/rockchip/rk3588/kernel/drivers/media/i2c/
H A Ddw9763.c273 ret = dw9763_write_reg(client, DW9763_RING_PD_CONTROL_REG, 0x00, 1); in dw9763t_init()
/device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/ispp/
H A Dstream_v20.c280 rkispp_set_bits(dev, RKISPP_FEC_CORE_CTRL, 0x00, SW_FEC_EN); in fec_work_event()
/foundation/ability/ability_runtime/test/fuzztest/napicommonwant_fuzzer/
H A Dnapicommonwant_fuzzer.cpp378 (void)memset_s(ch, size + 1, 0x00, size + 1); in LLVMFuzzerTestOneInput()
/foundation/graphic/graphic_3d/lume/LumeRender/src/gles/
H A Dwgl_state.cpp522 &plat_.deviceProperties, sizeof(plat_.deviceProperties), 0x00, sizeof(plat_.deviceProperties)); in GlInitialize()
/foundation/multimedia/audio_framework/frameworks/native/examples/
H A Dpa_stream_test.cpp154 char path[PATH_MAX] = { 0x00 }; in OpenSpkFile()

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