| /third_party/ffmpeg/libavformat/ |
| H A D | mxf.h | 95 #define FF_MXF_MasteringDisplayPrimaries { FF_MXF_MasteringDisplay_PREFIX,0x01,0x00,0x00 }
96 #define FF_MXF_MasteringDisplayWhitePointChromaticity { FF_MXF_MasteringDisplay_PREFIX,0x02,0x00,0x00 }
97 #define FF_MXF_MasteringDisplayMaximumLuminance { FF_MXF_MasteringDisplay_PREFIX,0x03,0x00,0x00 }
98 #define FF_MXF_MasteringDisplayMinimumLuminance { FF_MXF_MasteringDisplay_PREFIX,0x04,0x00,0x00 }
|
| H A D | a64.c | 32 0x00, //load in a64_write_header()
34 0x00, //mode in a64_write_header()
35 0x00, //charset_lifetime (multi only) in a64_write_header()
36 0x00 //fps in 50/fps; in a64_write_header()
46 header[2] = 0x00; in a64_write_header()
|
| /third_party/libwebsockets/lib/roles/listen/ |
| H A D | ops-listen.c | 192 /* LWS_ROPS_pt_init_destroy */ 0x00,
194 /* LWS_ROPS_destroy_vhost */ 0x00,
200 /* LWS_ROPS_tx_credit */ 0x00,
202 /* LWS_ROPS_encapsulation_parent */ 0x00,
204 /* LWS_ROPS_close_via_role_protocol */ 0x00,
206 /* LWS_ROPS_close_kill_connection */ 0x00,
208 /* LWS_ROPS_adoption_bind */ 0x00,
210 /* LWS_ROPS_issue_keepalive */ 0x00,
|
| /third_party/node/test/fixtures/wpt/encoding/legacy-mb-japanese/shift_jis/ |
| H A D | sjis-decoder.js | 22 var sjisLead = 0x00;
30 if (byte == endofstream && sjisLead != 0x00) {
31 sjisLead = 0x00;
35 if (byte == endofstream && sjisLead == 0x00) {
39 if (sjisLead != 0x00) {
42 sjisLead = 0x00;
55 if (cp == null && byte >= 0x00 && byte <= 0x7f) {
65 if ((byte >= 0x00 && byte <= 0x7f) || byte == 0x80) {
|
| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt76x0/ |
| H A D | initvals_phy.h | 17 { MT_RF(0, 5), 0x00 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
23 { MT_RF(0, 11), 0x00 },
24 { MT_RF(0, 12), 0x00 },
26 { MT_RF(0, 13), 0x00 },
27 { MT_RF(0, 14), 0x00 },
28 { MT_RF(0, 15), 0x00 },
33 { MT_RF(0, 23), 0x00 },
[all...] |
| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt76x0/ |
| H A D | initvals_phy.h | 17 { MT_RF(0, 5), 0x00 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
23 { MT_RF(0, 11), 0x00 },
24 { MT_RF(0, 12), 0x00 },
26 { MT_RF(0, 13), 0x00 },
27 { MT_RF(0, 14), 0x00 },
28 { MT_RF(0, 15), 0x00 },
33 { MT_RF(0, 23), 0x00 },
[all...] |
| /kernel/linux/linux-5.10/sound/soc/sh/rcar/ |
| H A D | dma.c | 15 #define PDMASAR 0x00
332 0x00, 0x01, 0x02, 0x03, 0x39, 0x3a, 0x3b, 0x3c,
342 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
344 0x0f, 0x00,
[all...] |
| /kernel/linux/linux-6.6/sound/soc/sh/rcar/ |
| H A D | dma.c | 15 #define PDMASAR 0x00
342 0x00, 0x01, 0x02, 0x03, 0x39, 0x3a, 0x3b, 0x3c,
352 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
354 0x0f, 0x00,
[all...] |
| /kernel/linux/linux-5.10/drivers/media/usb/pwc/ |
| H A D | pwc-kiara.c | 85 {1, 146, 0, {0x1D, 0xF4, 0x30, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x92, 0x00, 0x80}},
86 {1, 146, 0, {0x1D, 0xF4, 0x30, 0x00, 0x00, 0x00, 0x00,
[all...] |
| /kernel/linux/linux-6.6/drivers/media/usb/pwc/ |
| H A D | pwc-kiara.c | 85 {1, 146, 0, {0x1D, 0xF4, 0x30, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x92, 0x00, 0x80}},
86 {1, 146, 0, {0x1D, 0xF4, 0x30, 0x00, 0x00, 0x00, 0x00,
[all...] |
| /kernel/linux/linux-5.10/arch/arm/include/asm/hardware/ |
| H A D | locomo.h | 20 #define LOCOMO_VER 0x00
58 #define LOCOMO_SPIMD 0x00 /* SPI mode setting */
109 #define LOCOMO_KIB 0x00 /* KIB level */
116 #define LOCOMO_ALS 0x00 /* Adjust light cycle */
123 #define LOCOMO_TC 0x00 /* TFT control signal */
128 #define LOCOMO_ACC 0x00 /* Audio clock */
133 #define LOCOMO_ACC_XSEL0 0x00
137 #define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
153 #define LOCOMO_LPT0 0x00
|
| /kernel/linux/linux-6.6/arch/arm/include/asm/hardware/ |
| H A D | locomo.h | 20 #define LOCOMO_VER 0x00
58 #define LOCOMO_SPIMD 0x00 /* SPI mode setting */
109 #define LOCOMO_KIB 0x00 /* KIB level */
116 #define LOCOMO_ALS 0x00 /* Adjust light cycle */
123 #define LOCOMO_TC 0x00 /* TFT control signal */
128 #define LOCOMO_ACC 0x00 /* Audio clock */
133 #define LOCOMO_ACC_XSEL0 0x00
137 #define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
153 #define LOCOMO_LPT0 0x00
|
| /kernel/linux/linux-6.6/arch/arm/mach-omap1/ |
| H A D | hardware.h | 122 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
130 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
138 #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
146 #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
154 #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
162 #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
170 #define IRQ_ITR_REG_OFFSET 0x00
216 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
218 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
|
| /kernel/linux/linux-5.10/drivers/media/i2c/smiapp/ |
| H A D | smiapp-quirk.c | 68 { 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */ in jt8ew9_post_poweron()
77 { 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */ in jt8ew9_post_poweron()
113 * 0x00 - HS mode, 0x01 - LP11 in imx125es_post_poweron()
116 { 0x302d, 0x00 }, in imx125es_post_poweron()
143 { 0x3237, 0x00 }, /* For control of pulse timing for ADC */ in jt8ev1_post_poweron()
147 { 0x3304, 0x00 }, in jt8ev1_post_poweron()
153 { 0x3355, 0x00 }, in jt8ev1_post_poweron()
162 { 0x30ae, 0x00 }, /* For control of ADC clock */ in jt8ev1_post_poweron()
184 return smiapp_write_8(sensor, 0x3328, 0x00); in jt8ev1_pre_streamon()
200 rval = smiapp_write_8(sensor, 0x3205, 0x00); in jt8ev1_post_streamoff()
[all...] |
| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt7601u/ |
| H A D | initvals.h | 21 { 86, 0x00 },
23 { 92, 0x00 },
24 { 103, 0x00 },
38 { 99, 0x50 }, { 101, 0x00 }, { 103, 0xc0 }, { 104, 0x92 },
51 { 195, 0x00 }, { 196, 0x00 },
81 { 195, 0x85 }, { 196, 0x00 },
82 { 195, 0x86 }, { 196, 0x00 },
100 { 152, 0x23 }, { 153, 0x41 }, { 154, 0x00 }, { 155, 0x4f },
|
| /kernel/linux/linux-6.6/drivers/media/i2c/ccs/ |
| H A D | ccs-quirk.c | 53 { 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */ in jt8ew9_post_poweron()
62 { 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */ in jt8ew9_post_poweron()
98 * 0x00 - HS mode, 0x01 - LP11 in imx125es_post_poweron()
101 { 0x302d, 0x00 }, in imx125es_post_poweron()
127 { 0x3237, 0x00 }, /* For control of pulse timing for ADC */ in jt8ev1_post_poweron()
131 { 0x3304, 0x00 }, in jt8ev1_post_poweron()
137 { 0x3355, 0x00 }, in jt8ev1_post_poweron()
146 { 0x30ae, 0x00 }, /* For control of ADC clock */ in jt8ev1_post_poweron()
168 return ccs_write_addr(sensor, 0x3328, 0x00); in jt8ev1_pre_streamon()
184 rval = ccs_write_addr(sensor, 0x3205, 0x00); in jt8ev1_post_streamoff()
[all...] |
| /kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt7601u/ |
| H A D | initvals.h | 21 { 86, 0x00 },
23 { 92, 0x00 },
24 { 103, 0x00 },
38 { 99, 0x50 }, { 101, 0x00 }, { 103, 0xc0 }, { 104, 0x92 },
51 { 195, 0x00 }, { 196, 0x00 },
81 { 195, 0x85 }, { 196, 0x00 },
82 { 195, 0x86 }, { 196, 0x00 },
100 { 152, 0x23 }, { 153, 0x41 }, { 154, 0x00 }, { 155, 0x4f },
|
| /kernel/linux/linux-5.10/drivers/media/usb/gspca/ |
| H A D | pac207.c | 82 {0x00, 0x00, 0x00, 0x70, 0xa0, 0xf8, 0x00, 0x00},
83 {0x32, 0x00, 0x96, 0x00, 0xa2, 0x02, 0xaf, 0x00},
99 0x00, index, in pac207_write_regs()
116 err = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0x00, in pac207_write_reg()
[all...] |
| /kernel/linux/linux-5.10/drivers/staging/comedi/drivers/ |
| H A D | adv_pci_dio.c | 106 .sdi[1] = { 16, 0x00, }, /* ISO DI 0-15 */
108 .sdo[1] = { 16, 0x00, }, /* ISO DO 0-15 */
114 .sdi[1] = { 32, 0x00, }, /* ISO DI 0-31 */
120 .sdo[1] = { 32, 0x00, }, /* ISO DO 0-31 */
126 .sdi[0] = { 32, 0x00, }, /* DI 0-31 */
127 .sdo[0] = { 32, 0x00, }, /* DO 0-31 */
134 .sdi[1] = { 16, 0x00, }, /* ISO DI 0-15 */
135 .sdo[1] = { 16, 0x00, }, /* ISO DO 0-15 */
141 .sdio[0] = { 2, 0x00, }, /* 8255 DIO */
147 .sdi[1] = { 16, 0x00, }, /* IS
[all...] |
| /kernel/linux/linux-6.6/drivers/media/usb/gspca/ |
| H A D | pac207.c | 82 {0x00, 0x00, 0x00, 0x70, 0xa0, 0xf8, 0x00, 0x00},
83 {0x32, 0x00, 0x96, 0x00, 0xa2, 0x02, 0xaf, 0x00},
99 0x00, index, in pac207_write_regs()
116 err = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), 0x00, in pac207_write_reg()
[all...] |
| /kernel/linux/linux-6.6/drivers/staging/vt6656/ |
| H A D | rf.c | 37 {0x00, 0xff, 0xf3},
38 {0x00, 0x05, 0xa4},
42 {0x00, 0x06, 0x88},
44 {0x00, 0xdb, 0xba},
45 {0x00, 0x09, 0x9b},
47 {0x00, 0x00, 0x0d},
48 {0x00, 0x58, 0x0f}
91 {0x00, 0x61, 0xa5},
93 {0x00,
[all...] |
| /kernel/linux/linux-5.10/drivers/media/usb/em28xx/ |
| H A D | em28xx-dvb.c | 500 {{ 0x06, 0x02, 0x00, 0x31 }, 4}, in hauppauge_hvr930c_init()
502 {{ 0x01, 0x02, 0x00, 0xc6 }, 4}, in hauppauge_hvr930c_init()
503 {{ 0x01, 0x00 }, 2}, in hauppauge_hvr930c_init()
504 {{ 0x01, 0x00, 0xff, 0xaf }, 4}, in hauppauge_hvr930c_init()
505 {{ 0x01, 0x00, 0x03, 0xa0 }, 4}, in hauppauge_hvr930c_init()
506 {{ 0x01, 0x00 }, 2}, in hauppauge_hvr930c_init()
507 {{ 0x01, 0x00, 0x73, 0xaf }, 4}, in hauppauge_hvr930c_init()
508 {{ 0x04, 0x00 }, 2}, in hauppauge_hvr930c_init()
509 {{ 0x00, 0x04 }, 2}, in hauppauge_hvr930c_init()
510 {{ 0x00, in hauppauge_hvr930c_init()
[all...] |
| /kernel/linux/linux-6.6/drivers/media/usb/em28xx/ |
| H A D | em28xx-dvb.c | 497 {{ 0x06, 0x02, 0x00, 0x31 }, 4}, in hauppauge_hvr930c_init()
499 {{ 0x01, 0x02, 0x00, 0xc6 }, 4}, in hauppauge_hvr930c_init()
500 {{ 0x01, 0x00 }, 2}, in hauppauge_hvr930c_init()
501 {{ 0x01, 0x00, 0xff, 0xaf }, 4}, in hauppauge_hvr930c_init()
502 {{ 0x01, 0x00, 0x03, 0xa0 }, 4}, in hauppauge_hvr930c_init()
503 {{ 0x01, 0x00 }, 2}, in hauppauge_hvr930c_init()
504 {{ 0x01, 0x00, 0x73, 0xaf }, 4}, in hauppauge_hvr930c_init()
505 {{ 0x04, 0x00 }, 2}, in hauppauge_hvr930c_init()
506 {{ 0x00, 0x04 }, 2}, in hauppauge_hvr930c_init()
507 {{ 0x00, in hauppauge_hvr930c_init()
[all...] |
| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| H A D | intersil.h | 5 #define INTERSIL_FREQ_32K 0x00
11 #define INTERSIL_12H_MODE 0x00
15 #define INTERSIL_STOP 0x00
20 #define INTERSIL_INT_DISABLE 0x00
23 #define INTERSIL_MODE_NORMAL 0x00
|
| /kernel/linux/linux-6.6/arch/m68k/include/asm/ |
| H A D | intersil.h | 5 #define INTERSIL_FREQ_32K 0x00
11 #define INTERSIL_12H_MODE 0x00
15 #define INTERSIL_STOP 0x00
20 #define INTERSIL_INT_DISABLE 0x00
23 #define INTERSIL_MODE_NORMAL 0x00
|