/third_party/mesa3d/src/gallium/frontends/clover/nir/ |
H A D | invocation.cpp | 167 deref->dest.ssa.bit_size); in clover_nir_lower_images() 168 nir_ssa_def_rewrite_uses(&deref->dest.ssa, loc); in clover_nir_lower_images() 194 nir_ssa_def *offset = nir_u2u32(&b, tex->src[i].src.ssa); in clover_nir_lower_images() 241 nir_ssa_def *offset = nir_u2u32(&b, intrin->src[0].ssa); in clover_nir_lower_images()
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/third_party/mesa3d/src/microsoft/spirv_to_dxil/ |
H A D | dxil_spirv_nir.c | 138 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load_data); in lower_shader_system_values() 227 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load_data); in lower_load_push_constant() 393 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_imm_float(builder, 1.0)); in discard_psiz_access() 466 nir_ssa_def_rewrite_uses(&intr->dest.ssa, undef); in kill_undefined_varyings()
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/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/ |
H A D | regalloc.c | 93 reg = &dest->ssa; in ppir_regalloc_update_reglist_ssa() 247 alu_dest->ssa.num_components = num_components; in ppir_update_spilled_src() 248 alu_dest->ssa.spilled = true; in ppir_update_spilled_src() 251 list_addtail(&alu_dest->ssa.list, &comp->reg_list); in ppir_update_spilled_src()
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H A D | node.c | 378 snprintf(node->name, sizeof(node->name), "ssa%d", index); in ppir_node_create() 518 printf("ssa%d", dest->ssa.index); in ppir_node_print_dest() 534 printf("ssa node %d", src->node->index); in ppir_node_print_src() 536 printf("ssa idx %d", src->ssa ? src->ssa->index : -1); in ppir_node_print_src()
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H A D | lower.c | 243 move_src->ssa = src0->ssa; in ppir_lower_select() 440 zero->dest.ssa.num_components = 1; in ppir_lower_branch()
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H A D | node_to_instr.c | 111 alu->dest.ssa.num_components == 1) { in ppir_do_one_node_to_instr() 157 dest->ssa.index = -1; in ppir_do_one_node_to_instr() 192 /* update succ from ^const to ssa mov output */ in ppir_do_one_node_to_instr()
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/third_party/mesa3d/src/gallium/drivers/iris/ |
H A D | iris_program.c | 243 assert(deref->arr.index.ssa); in get_aoa_deref_offset() 517 unsigned load_size = intrin->dest.ssa.num_components * in iris_setup_uniforms() 518 intrin->dest.ssa.bit_size / 8; in iris_setup_uniforms() 519 unsigned load_align = intrin->dest.ssa.bit_size / 8; in iris_setup_uniforms() 542 intrin->dest.ssa.num_components, in iris_setup_uniforms() 543 intrin->dest.ssa.bit_size); in iris_setup_uniforms() 545 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, in iris_setup_uniforms() 652 offset = nir_iadd_imm(&b, intrin->src[0].ssa, in iris_setup_uniforms() 661 nir_load_ubo(&b, intrin->dest.ssa.num_components, intrin->dest.ssa in iris_setup_uniforms() [all...] |
/third_party/mesa3d/src/amd/vulkan/ |
H A D | radv_meta_resolve_fs.c | 276 nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa; in build_depth_stencil_resolve_fragment_shader() 296 nir_ssa_def *outval = &tex->dest.ssa; in build_depth_stencil_resolve_fragment_shader() 319 outval = nir_fadd(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_fragment_shader() 323 outval = nir_fmin(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_fragment_shader() 325 outval = nir_umin(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_fragment_shader() 329 outval = nir_fmax(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_fragment_shader() 331 outval = nir_umax(&b, outval, &tex_add->dest.ssa); in build_depth_stencil_resolve_fragment_shader()
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H A D | radv_shader.c | 133 const unsigned bit_size = alu->dest.dest.ssa.bit_size; in vectorize_vec2_16bit() 341 def = nir_ieq_imm(&b, intrin->src[0].ssa, 0); in lower_intrinsics() 344 def = nir_ior(&b, intrin->src[0].ssa, intrin->src[1].ssa); in lower_intrinsics() 355 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, def); in lower_intrinsics() 481 nir_ssa_scalar scalar_idx = nir_ssa_scalar_resolved(intr->src[1].ssa, 3); in radv_force_primitive_shading_rate() 495 nir_ssa_def *pos_w = nir_channel(&b, intr->src[1].ssa, 3); in radv_force_primitive_shading_rate() 564 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, def); in radv_lower_fs_intrinsics() 574 if (!(nir_ssa_def_components_read(&intrin->dest.ssa) & (1 << 2))) in radv_lower_fs_intrinsics() 577 nir_ssa_def *frag_z = nir_channel(&b, &intrin->dest.ssa, in radv_lower_fs_intrinsics() [all...] |
H A D | radv_meta_blit.c | 103 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa; in build_nir_copy_fragment_shader() 123 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf); in build_nir_copy_fragment_shader() 151 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa; in build_nir_copy_fragment_shader_depth() 171 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1); in build_nir_copy_fragment_shader_depth() 199 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa; in build_nir_copy_fragment_shader_stencil() 219 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1); in build_nir_copy_fragment_shader_stencil()
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/third_party/ffmpeg/tests/fate/ |
H A D | subtitles.mak | 16 FATE_SUBTITLES_ASS-$(CONFIG_ASS_DEMUXER) += fate-sub-ssa-to-ass-remux 17 fate-sub-ssa-to-ass-remux: CMD = fmtstdout ass -i $(TARGET_SAMPLES)/sub/a9-misc.ssa -c copy
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/third_party/mesa3d/src/panfrost/vulkan/ |
H A D | panvk_vX_shader.c | 89 nir_ssa_def_rewrite_uses(&intr->dest.ssa, constant); in panvk_inline_blend_constants() 196 intr->src[0].ssa, in panvk_lower_load_push_constant() 201 nir_ssa_def_rewrite_uses(&intr->dest.ssa, ubo_load); in panvk_lower_load_push_constant()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
H A D | ir2.c | 154 * but for instrs which have 2 ssa/reg srcs, then its not ideal 200 ins->ssa.idx = reg->idx; in scalarize_case1() 201 ins->ssa.ncomp = 1; in scalarize_case1() 202 ins->ssa.comp[0].c = comp; in scalarize_case1() 272 /* don't reorder non-ssa write before read */ in sched_next()
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/third_party/mesa3d/src/gallium/auxiliary/nir/ |
H A D | nir_draw_helpers.c | 92 nir_ssa_def *condition = nir_f2b32(b, nir_channel(b, &tex->dest.ssa, 3)); in nir_lower_pstipple_block() 174 nir_ssa_def *out_input = intrin->src[1].ssa; in nir_lower_aaline_block() 269 nir_ssa_def *out_input = intrin->src[1].ssa; in nir_lower_aapoint_block()
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/third_party/mesa3d/src/compiler/nir/ |
H A D | nir_lower_point_smooth.c | 80 intr->src[0].ssa); in lower_point_smooth()
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H A D | nir_lower_single_sampled.c | 87 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, lowered); in lower_single_sampled_instr()
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H A D | nir_lower_fragcolor.c | 69 nir_ssa_def *frag_color = instr->src[1].ssa; in lower_fragcolor_instr()
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H A D | nir_lower_task_shader.c | 59 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load); in lower_nv_task_output() 66 nir_ssa_def *store_val = intrin->src[0].ssa; in lower_nv_task_output()
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H A D | nir_opt_dead_cf.c | 104 def = phi_src->src.ssa; in opt_constant_if() 109 nir_ssa_def_rewrite_uses(&phi->dest.ssa, def); in opt_constant_if()
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/third_party/mesa3d/src/freedreno/ir3/ |
H A D | ir3_nir_lower_load_barycentric_at_offset.c | 41 nir_ssa_def *off = intr->src[0].ssa; in ir3_nir_lower_load_barycentric_at_offset_instr()
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H A D | ir3_nir_lower_64b.c | 109 nir_ssa_def *def = &intr->dest.ssa; in lower_64b_intrinsics() 152 components[i] = nir_pack_64_2x32(b, &load->dest.ssa); in lower_64b_intrinsics()
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/third_party/mesa3d/src/panfrost/midgard/ |
H A D | midgard_errata_lod.c | 59 nir_ssa_def *params = &l->dest.ssa; in nir_lod_errata_instr()
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H A D | midgard_address.c | 256 struct mir_address match = mir_match_offset(offset->ssa, first_free, true); in mir_set_offset() 295 struct mir_address match = mir_match_offset(src->ssa, false, false); in mir_set_ubo_offset()
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/third_party/mesa3d/src/microsoft/compiler/ |
H A D | nir_to_dxil.c | 1692 store_ssa_def(struct ntd_context *ctx, nir_ssa_def *ssa, unsigned chan, in store_ssa_def() argument 1695 assert(ssa->index < ctx->num_defs); in store_ssa_def() 1696 assert(chan < ssa->num_components); in store_ssa_def() 1699 if (ctx->defs[ssa->index].chans[chan]) { in store_ssa_def() 1700 const struct dxil_type *expect_type = dxil_value_get_type(ctx->defs[ssa->index].chans[chan]); in store_ssa_def() 1705 ctx->defs[ssa->index].chans[chan] = value; in store_ssa_def() 1714 store_ssa_def(ctx, &dest->ssa, chan, value); in store_dest_value() 1752 get_src_ssa(struct ntd_context *ctx, const nir_ssa_def *ssa, unsigned chan) in get_src_ssa() argument 1754 assert(ssa->index < ctx->num_defs); in get_src_ssa() 1755 assert(chan < ssa in get_src_ssa() [all...] |
/third_party/mesa3d/src/gallium/drivers/d3d12/ |
H A D | d3d12_lower_image_casts.c | 215 value = &intr->dest.ssa; in lower_image_cast_instr() 220 value = intr->src[3].ssa; in lower_image_cast_instr()
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