/third_party/mesa3d/src/intel/compiler/ |
H A D | brw_nir_lower_cs_intrinsics.c | 60 if (intrinsic->dest.ssa.bit_size == 64) { in lower_cs_intrinsics_convert_block() 61 intrinsic->dest.ssa.bit_size = 32; in lower_cs_intrinsics_convert_block() 62 sysval = nir_u2u64(b, &intrinsic->dest.ssa); in lower_cs_intrinsics_convert_block() 63 nir_ssa_def_rewrite_uses_after(&intrinsic->dest.ssa, in lower_cs_intrinsics_convert_block() 248 if (intrinsic->dest.ssa.bit_size == 64) in lower_cs_intrinsics_convert_block() 251 nir_ssa_def_rewrite_uses(&intrinsic->dest.ssa, sysval); in lower_cs_intrinsics_convert_block()
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H A D | brw_nir_lower_intersection_shader.c | 98 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, in lower_any_hit_for_intersection() 104 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, in lower_any_hit_for_intersection() 211 &nir_build_deref_var(b, commit_tmp)->dest.ssa, in brw_nir_lower_intersection_shader() 233 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, in brw_nir_lower_intersection_shader()
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/third_party/mesa3d/src/compiler/nir/ |
H A D | nir_opt_load_store_vectorize.c | 171 * "offset_defs" is sorted in ascenting order by the ssa definition's index. 285 entry->intrin->src[entry->info->value_src].ssa->bit_size : in get_bit_size() 286 entry->intrin->dest.ssa.bit_size; in get_bit_size() 428 nir_ssa_def *index = deref->arr.index.ssa; in create_entry_key_from_deref() 452 key->resource = deref->parent.ssa; in create_entry_key_from_deref() 598 intrin->src[entry->info->base_src].ssa : NULL; in create_entry() 610 entry->key->resource = intrin->src[entry->info->resource_src].ssa; in create_entry() 648 return nir_build_deref_cast(b, &deref->dest.ssa, deref->modes, type, 0); in cast_deref() 710 deref->dest.ssa.bit_size); in subtract_deref() 724 deref = nir_build_deref_cast(b, &deref->dest.ssa, dere in subtract_deref() [all...] |
H A D | nir_lower_int64.c | 1008 if (alu->src[0].src.ssa->bit_size != 64) in should_lower_int64_alu_instr() 1014 assert(alu->src[1].src.ssa->bit_size == in should_lower_int64_alu_instr() 1015 alu->src[2].src.ssa->bit_size); in should_lower_int64_alu_instr() 1016 if (alu->src[1].src.ssa->bit_size != 64) in should_lower_int64_alu_instr() 1027 assert(alu->src[0].src.ssa->bit_size == in should_lower_int64_alu_instr() 1028 alu->src[1].src.ssa->bit_size); in should_lower_int64_alu_instr() 1029 if (alu->src[0].src.ssa->bit_size != 64) in should_lower_int64_alu_instr() 1035 if (alu->src[0].src.ssa->bit_size != 64) in should_lower_int64_alu_instr() 1042 if (alu->dest.dest.ssa.bit_size != 64) in should_lower_int64_alu_instr() 1052 if (alu->src[0].src.ssa in should_lower_int64_alu_instr() [all...] |
H A D | nir_lower_bitmap.c | 100 tex->src[0].src = nir_src_for_ssa(&tex_deref->dest.ssa); in lower_bitmap() 102 tex->src[1].src = nir_src_for_ssa(&tex_deref->dest.ssa); in lower_bitmap() 112 cond = nir_f2b(b, nir_channel(b, &tex->dest.ssa, in lower_bitmap()
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H A D | nir_serialize.c | 526 header.any.object_idx = write_lookup_object(ctx, src->ssa); in write_src_full() 556 src->ssa = read_lookup_object(ctx, header.any.object_idx); in read_src() 577 } ssa; member 697 dest.ssa.is_ssa = dst->is_ssa; in write_dest() 699 dest.ssa.num_components = in write_dest() 700 encode_num_components_in_3bits(dst->ssa.num_components); in write_dest() 701 dest.ssa.bit_size = encode_bit_size_3bits(dst->ssa.bit_size); in write_dest() 702 dest.ssa.divergent = dst->ssa in write_dest() [all...] |
H A D | nir_lower_scratch.c | 55 unsigned bit_size = intrin->dest.ssa.bit_size; in lower_load_store() 61 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, value); in lower_load_store() 66 nir_ssa_def *value = intrin->src[1].ssa; in lower_load_store() 80 nir_foreach_use(src, &deref->dest.ssa) { in only_used_for_load_store()
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H A D | nir_liveness.c | 83 BITSET_SET(live, src->ssa->index); in set_src_live() 120 set_ssa_def_dead(&phi->dest.ssa, live); in propagate_across_edge() 276 return !src->is_ssa || src->ssa != (nir_ssa_def *)def; in src_does_not_use_def() 296 following_if->condition.ssa == def) in search_for_use_after_instr()
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H A D | nir_lower_io_arrays_to_elements.c | 121 nir_ssa_def *zero = nir_imm_zero(b, intr->dest.ssa.num_components, in lower_array() 122 intr->dest.ssa.bit_size); in lower_array() 123 nir_ssa_def_rewrite_uses(&intr->dest.ssa, in lower_array() 175 element_intr->src[0] = nir_src_for_ssa(&element_deref->dest.ssa); in lower_array() 179 intr->num_components, intr->dest.ssa.bit_size, NULL); in lower_array() 187 nir_ssa_def_rewrite_uses(&intr->dest.ssa, in lower_array() 188 &element_intr->dest.ssa); in lower_array()
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/third_party/mesa3d/src/amd/common/ |
H A D | ac_nir_lower_ngg.c | 38 nir_ssa_def *ssa; member 529 nir_ssa_def *store_val = intrin->src[0].ssa; in remove_culling_shader_output() 613 nir_ssa_def *store_val = intrin->src[0].ssa; in remove_extra_pos_output() 639 vec_comps[i] = alu->src[i].src.ssa; in remove_extra_pos_output() 680 nir_ssa_def_rewrite_uses(state->overwrite_args->src[idx].ssa, undef_arg); in remove_compacted_arg() 862 analyze_shader_before_culling_walk(nir_ssa_def *ssa, in analyze_shader_before_culling_walk() argument 866 nir_instr *instr = ssa->parent_instr; in analyze_shader_before_culling_walk() 899 analyze_shader_before_culling_walk(alu->src[i].src.ssa, flag, nogs_state); in analyze_shader_before_culling_walk() 907 analyze_shader_before_culling_walk(phi_src->src.ssa, flag, nogs_state); in analyze_shader_before_culling_walk() 933 nir_ssa_def *store_val = intrin->src[0].ssa; in analyze_shader_before_culling() 976 nir_ssa_def *ssa = NULL; save_reusable_variables() local [all...] |
H A D | ac_nir_lower_tess_io_to_mem.c | 259 nir_store_shared(b, intrin->src[0].ssa, off, .write_mask = write_mask, in lower_ls_output_store() 291 nir_instr *vertex_index_instr = vertex_index_src->ssa->parent_instr; in filter_load_tcs_per_vertex_input() 307 nir_ssa_def *vertex_index = nir_get_io_arrayed_index_src(instr)->ssa; in hs_per_vertex_input_lds_offset() 417 return nir_load_shared(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size, off, in lower_hs_per_vertex_input_load() 430 nir_ssa_def *store_val = intrin->src[0].ssa; in lower_hs_output_store() 474 return nir_load_shared(b, intrin->dest.ssa.num_components, intrin->dest.ssa.bit_size, off, in lower_hs_output_load() 642 return nir_load_buffer_amd(b, intrin->dest.ssa.num_components, intrin->dest.ssa in lower_tes_input_load() [all...] |
H A D | ac_nir_lower_taskmesh_io_to_mem.c | 68 if (s->hw_workgroup_id == &intrin->dest.ssa) in replace_workgroup_id_use_first_task() 281 nir_ssa_def *dimensions = intrin->src[0].ssa; in lower_task_launch_mesh_workgroups() 302 nir_ssa_def *store_val = intrin->src[0].ssa; in lower_task_payload_store() 303 nir_ssa_def *addr = intrin->src[1].ssa; in lower_task_payload_store() 321 unsigned num_components = intrin->dest.ssa.num_components; in lower_taskmesh_payload_load() 322 unsigned bit_size = intrin->dest.ssa.bit_size; in lower_taskmesh_payload_load() 329 nir_ssa_def *addr = intrin->src[0].ssa; in lower_taskmesh_payload_load()
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/third_party/mesa3d/src/microsoft/clc/ |
H A D | clc_compiler.c | 147 nir_foreach_use_safe(src, &context->deref->dest.ssa) { in clc_lower_input_image_deref() 220 nir_ssa_def_rewrite_uses(&intrinsic->dest.ssa, *cached_deref); in clc_lower_input_image_deref() 311 intrinsic->dest.ssa.bit_size = 32; in clc_lower_64bit_semantics() 314 nir_ssa_def *i64 = nir_u2u64(&b, &intrinsic->dest.ssa); in clc_lower_64bit_semantics() 316 &intrinsic->dest.ssa, in clc_lower_64bit_semantics() 348 assert(sampler_src->is_ssa && sampler_src->ssa->parent_instr->type == nir_instr_type_deref); in clc_lower_nonnormalized_samplers() 350 nir_instr_as_deref(sampler_src->ssa->parent_instr)); in clc_lower_nonnormalized_samplers() 570 unsigned comp_size = intrin->dest.ssa.bit_size / 8; in split_unaligned_load() 571 unsigned num_comps = intrin->dest.ssa.num_components; in split_unaligned_load() 578 nir_deref_instr *cast = nir_build_deref_cast(b, &ptr->dest.ssa, pt in split_unaligned_load() [all...] |
/third_party/mesa3d/src/freedreno/ir3/ |
H A D | ir3_cp.c | 67 struct ir3_instruction *src_instr = ssa(src); in is_eligible_mov() 102 struct ir3_instruction *cond = ssa(cmp->srcs[0]); in is_foldable_double_cmp() 150 struct ir3_instruction *srcsrc = ssa(src->srcs[0]); in combine_flags() 341 * register with a non-ssa src) or collapsing mov's from relative 349 struct ir3_instruction *src = ssa(reg); in reg_cp() 352 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */ in reg_cp() 532 struct ir3_instruction *src_instr = ssa(reg); in eliminate_output_mov() 559 struct ir3_instruction *src = ssa(reg); in instr_cp() 615 struct ir3_instruction *cond = ssa(instr->srcs[0]); in instr_cp() 649 struct ir3_instruction *samp_tex = ssa(inst in instr_cp() [all...] |
H A D | ir3_nir.h | 42 int ir3_nir_coord_offset(nir_ssa_def *ssa); 89 if (src.ssa->parent_instr->type != nir_instr_type_intrinsic) in ir3_bindless_resource() 92 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src.ssa->parent_instr); in ir3_bindless_resource()
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/third_party/mesa3d/src/amd/llvm/ |
H A D | ac_nir_to_llvm.c | 87 return nir->ssa_defs[src.ssa->index]; in get_src() 566 unsigned num_components = instr->dest.dest.ssa.num_components; in visit_alu() 568 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa); in visit_alu() 621 result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); in visit_alu() 799 result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); in visit_alu() 894 result = ac_build_frexp_mant(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size); in visit_alu() 897 if (instr->dest.dest.ssa.bit_size != 32) { in visit_alu() 923 if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) { in visit_alu() 925 result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); in visit_alu() 931 if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa in visit_alu() [all...] |
/third_party/mesa3d/src/compiler/spirv/ |
H A D | vtn_variables.c | 207 nir_ssa_def *ssa = vtn_ssa_value(b, link.id)->def; in vtn_access_link_as_ssa() local 208 if (ssa->bit_size != bit_size) in vtn_access_link_as_ssa() 209 ssa = nir_i2i(&b->nb, ssa, bit_size); in vtn_access_link_as_ssa() 210 return nir_imul_imm(&b->nb, ssa, stride); in vtn_access_link_as_ssa() 255 instr->num_components = instr->dest.ssa.num_components; in vtn_variable_resource_index() 258 return &instr->dest.ssa; in vtn_variable_resource_index() 278 instr->num_components = instr->dest.ssa.num_components; in vtn_resource_reindex() 281 return &instr->dest.ssa; in vtn_resource_reindex() 300 desc_load->num_components = desc_load->dest.ssa in vtn_descriptor_load() 1728 vtn_pointer_from_ssa(struct vtn_builder *b, nir_ssa_def *ssa, struct vtn_type *ptr_type) vtn_pointer_from_ssa() argument [all...] |
H A D | vtn_subgroup.c | 57 intrin->num_components = intrin->dest.ssa.num_components; in vtn_build_subgroup_instr() 68 dst->def = &intrin->dest.ssa; in vtn_build_subgroup_instr() 88 vtn_push_nir_ssa(b, w[2], &elect->dest.ssa); in vtn_handle_subgroup() 103 vtn_push_nir_ssa(b, w[2], &ballot->dest.ssa); in vtn_handle_subgroup() 123 vtn_push_nir_ssa(b, w[2], &intrin->dest.ssa); in vtn_handle_subgroup() 178 vtn_push_nir_ssa(b, w[2], &intrin->dest.ssa); in vtn_handle_subgroup() 271 vtn_push_nir_ssa(b, w[2], &intrin->dest.ssa); in vtn_handle_subgroup()
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/third_party/mesa3d/src/intel/vulkan/ |
H A D | anv_nir_add_base_work_group_id.c | 47 nir_ssa_def *id = nir_iadd(b, &load_id->dest.ssa, load_base); in anv_nir_add_base_work_group_id_instr() 49 nir_ssa_def_rewrite_uses_after(&load_id->dest.ssa, id, id->parent_instr); in anv_nir_add_base_work_group_id_instr()
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/third_party/mesa3d/src/broadcom/compiler/ |
H A D | v3d_nir_lower_robust_buffer_access.c | 45 nir_iand(b, &size->dest.ssa, nir_imm_int(b, 0xfffffffc)); in rewrite_offset() 49 nir_umin(b, instr->src[offset_src].ssa, aligned_buffer_size); in rewrite_offset() 99 nir_ssa_def *offset = nir_umin(b, instr->src[0].ssa, aligned_size); in lower_shared()
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H A D | v3d_nir_lower_scratch.c | 69 instr->dest.ssa.bit_size, NULL); in v3d_nir_lower_load_scratch() 77 chans[i] = &chan_instr->dest.ssa; in v3d_nir_lower_load_scratch() 81 nir_ssa_def_rewrite_uses(&instr->dest.ssa, result); in v3d_nir_lower_load_scratch()
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/third_party/mesa3d/src/microsoft/compiler/ |
H A D | dxil_nir_lower_int_samplers.c | 81 nir_ssa_def *ssa_src = nir_channels(b, tex->src[coord_index].src.ssa, in dx_get_texture_lod() 105 return nir_channel(b, &tql->dest.ssa, 0); in dx_get_texture_lod() 320 return &load->dest.ssa; in load_texel() 342 lod = tex->src[lod_index].src.ssa; in evalute_active_lod() 349 tex->src[ddx_index].src.ssa, in evalute_active_lod() 350 tex->src[ddy_index].src.ssa); in evalute_active_lod() 386 lod_bias = nir_fadd(b, lod_bias, tex->src[bias_index].src.ssa); in evalute_active_lod() 428 nir_ssa_def *old_coord = tex->src[coord_index].src.ssa; in lower_sample_to_txf_for_integer_tex_impl() 492 nir_ssa_def *offset = tex->src[offset_index].src.ssa; in lower_sample_to_txf_for_integer_tex_impl()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
H A D | ir2_nir.c | 224 * XXX dont do this for ssa in update_range() 240 float c[src.ssa->num_components]; in make_src() 241 nir_const_value_to_array(c, const_value, src.ssa->num_components, f32); in make_src() 242 return load_const(ctx, c, src.ssa->num_components); in make_src() 250 assert(ctx->ssa_map[src.ssa->index] >= 0); in make_src() 251 res.num = ctx->ssa_map[src.ssa->index]; in make_src() 253 reg = &ctx->instr[res.num].ssa; in make_src() 263 struct ir2_reg *reg = &instr->ssa; in set_index() 266 ctx->ssa_map[dst->ssa.index] = instr->idx; in set_index() 346 instr->ssa in instr_create_alu() [all...] |
/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_shader_nir.c | 37 alu->dest.dest.ssa.bit_size == 16 && in si_alu_to_scalar_filter() 38 alu->dest.dest.ssa.num_components == 2) in si_alu_to_scalar_filter() 220 return nir_ieq_imm(b, intrin->src[0].ssa, 0); in lower_intrinsic_instr() 222 return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa); in lower_intrinsic_instr()
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/third_party/mesa3d/src/gallium/drivers/llvmpipe/ |
H A D | lp_state_fs_analysis.c | 192 const nir_instr *parent = src->src.ssa[0].parent_instr; in get_nir_input_info() 204 parent = intrin->src->ssa->parent_instr; in get_nir_input_info() 257 const nir_instr *parent = texcoord->src.ssa->parent_instr; in get_texcoord_provenance() 312 nir_instr_as_load_const(intrin->src[0].ssa->parent_instr); in llvmpipe_nir_fn_is_linear_compat() 386 nir_instr_as_load_const(alu->src[s].src.ssa->parent_instr); in llvmpipe_nir_fn_is_linear_compat()
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