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/third_party/node/deps/v8/src/execution/s390/
H A Dsimulator-s390.cc2404 // Test src1 and src2 have opposite sign,
2409 #define CheckOverflowForIntAdd(src1, src2, type) \
2410 OverflowFromSigned<type>(src1 + src2, src1, src2, true);
2412 #define CheckOverflowForIntSub(src1, src2, type) \
2413 OverflowFromSigned<type>(src1 - src2, src1, src2, false);
2416 #define CheckOverflowForUIntAdd(src1, src2) \
2417 ((src1) + (src2) < (src1) || (src
3288 VectorBinaryOp(Simulator* sim, int dst, int src1, int src2, Operation op) VectorBinaryOp() argument
3434 VectorSum(Simulator* sim, int dst, int src1, int src2) VectorSum() argument
3528 VectorPack(Simulator* sim, int dst, int src1, int src2, bool saturate, const D& max = 0, const D& min = 0) VectorPack() argument
4189 int64_t src1 = get_simd_register_by_lane<int64_t>(r1, 0); EVALUATE() local
4400 FP_Type src1 = sim->get_fpr<FP_Type>(lhs); FPMinMaxForEachLane() local
4406 FP_Type src1 = sim->get_simd_register_by_lane<FP_Type>(lhs, i); FPMinMaxForEachLane() local
4446 VectorFPCompare(Simulator* sim, int dst, int src1, int src2, int m6, Operation op) VectorFPCompare() argument
[all...]
/third_party/ffmpeg/libavcodec/
H A Dmagicyuv.c94 static void magicyuv_median_pred16(uint16_t *dst, const uint16_t *src1, in magicyuv_median_pred16() argument
105 l = mid_pred(l, src1[i], (l + src1[i] - lt)) + diff[i]; in magicyuv_median_pred16()
107 lt = src1[i]; in magicyuv_median_pred16()
H A Dvp3dsp.c431 static void put_no_rnd_pixels_l2(uint8_t *dst, const uint8_t *src1, in put_no_rnd_pixels_l2() argument
439 a = AV_RN32(&src1[i * stride]); in put_no_rnd_pixels_l2()
442 a = AV_RN32(&src1[i * stride + 4]); in put_no_rnd_pixels_l2()
H A Ddcadsp.h85 void (*assemble_freq_bands)(int32_t *dst, int32_t *src0, int32_t *src1,
/third_party/ffmpeg/libswscale/
H A Dswscale_internal.h570 const uint8_t *src1, const uint8_t *src2, const uint8_t *src3,
608 const uint8_t *src1, const uint8_t *src2,
975 int dstWidth, const uint8_t *src1,
984 int dstWidth, const uint8_t *src1,
H A Drgb2rgb.c88 void (*interleaveBytes)(const uint8_t *src1, const uint8_t *src2, uint8_t *dst,
94 void (*vu9_to_vu12)(const uint8_t *src1, const uint8_t *src2,
99 void (*yvu9_to_yuy2)(const uint8_t *src1, const uint8_t *src2,
/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_emit.c139 .src1 = packed_src[0], in vector_to_scalar_alu()
361 alu->src1 = p; in mir_pack_vector_srcs()
631 unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]); in texture_word_from_instr() local
632 tex.in_reg_select = src1 & 1; in texture_word_from_instr()
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/utils/
H A Dcommon.c776 const u8 *src1, size_t src1_len, in merge_byte_arrays()
783 if (src1) { in merge_byte_arrays()
785 os_memcpy(res, src1, res_len); in merge_byte_arrays()
789 os_memcpy(res, src1, src1_len); in merge_byte_arrays()
775 merge_byte_arrays(u8 *res, size_t res_len, const u8 *src1, size_t src1_len, const u8 *src2, size_t src2_len) merge_byte_arrays() argument
/third_party/mesa3d/src/amd/compiler/
H A Daco_instruction_selection.cpp876 Temp src1 = get_alu_src(ctx, instr->src[swap_srcs ? 0 : 1]);
877 if (src1.type() == RegType::sgpr) {
880 src0 = src1;
881 src1 = t;
883 src1 = as_vgpr(ctx, src1);
887 Operand op[2] = {Operand(src0), Operand(src1)};
919 Temp src1 = get_alu_src(ctx, instr->src[1]);
921 if (src1.type() == RegType::sgpr) {
923 std::swap(src0, src1);
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/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qir.h526 struct qreg src0, struct qreg src1);
715 qir_SEL(struct vc4_compile *c, uint8_t cond, struct qreg src0, struct qreg src1) in qir_SEL() argument
718 qir_MOV_dest(c, t, src1); in qir_SEL()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp15 // $res = VALU $dpp_value [, src1]
19 // $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
32 // -> $combined_old = src1,
230 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in createDPPInst()
232 LLVM_DEBUG(dbgs() << " failed: src1 is illegal\n"); in createDPPInst()
323 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1); in createDPPInst()
325 LLVM_DEBUG(dbgs() << " failed: no src1 or it isn't a register\n"); in createDPPInst()
334 LLVM_DEBUG(dbgs() << " failed: src1 isn't a VGPR32 register\n"); in createDPPInst()
517 Use == TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in combineDPPMov()
H A DSIFoldOperands.cpp204 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) in updateOperand()
818 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane) in foldOperand()
837 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane) in foldOperand()
999 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1); in tryConstantFoldOp()
1109 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); in tryFoldInst()
1121 MI->RemoveOperand(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1)); in tryFoldInst()
1275 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1391 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
1420 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isOMod()
/kernel/linux/linux-5.10/arch/arc/include/asm/
H A Ddisasm.h85 int src1, src2, src3, dest, wb_reg; member
/kernel/linux/linux-6.6/arch/arc/include/asm/
H A Ddisasm.h85 int src1, src2, src3, dest, wb_reg; member
/third_party/ffmpeg/libavfilter/x86/
H A Dscene_sad.asm31 cglobal scene_sad, 6, 7, 2, src1, stride1, src2, stride2, width, end, x
/third_party/mbedtls/library/
H A Dconstant_time_internal.h476 * memcpy(dest, src1, len);
482 * It will always read len bytes from src1.
488 * \param src1 Secret. Pointer to copy from (if \p condition == MBEDTLS_CT_TRUE).
492 * This may be equal to \p dest, but may not overlap it in other ways. It may overlap with \p src1.
497 const unsigned char *src1,
/kernel/linux/linux-5.10/drivers/video/fbdev/
H A Ds3fb.c351 const u8 *src1, *src; in s3fb_iplan_imageblit() local
357 src1 = image->data; in s3fb_iplan_imageblit()
362 src = src1; in s3fb_iplan_imageblit()
369 src1 += image->width / 8; in s3fb_iplan_imageblit()
408 const u8 *src1, *src; in s3fb_cfb4_imageblit() local
414 src1 = image->data; in s3fb_cfb4_imageblit()
419 src = src1; in s3fb_cfb4_imageblit()
426 src1 += image->width / 8; in s3fb_cfb4_imageblit()
/kernel/linux/linux-6.6/drivers/video/fbdev/
H A Ds3fb.c352 const u8 *src1, *src; in s3fb_iplan_imageblit() local
358 src1 = image->data; in s3fb_iplan_imageblit()
363 src = src1; in s3fb_iplan_imageblit()
370 src1 += image->width / 8; in s3fb_iplan_imageblit()
409 const u8 *src1, *src; in s3fb_cfb4_imageblit() local
415 src1 = image->data; in s3fb_cfb4_imageblit()
420 src = src1; in s3fb_cfb4_imageblit()
427 src1 += image->width / 8; in s3fb_cfb4_imageblit()
/third_party/mesa3d/src/gallium/drivers/zink/nir_to_spirv/
H A Dnir_to_spirv.c127 SpvId src0, SpvId src1);
131 SpvId src0, SpvId src1, SpvId src2);
1704 emit_atomic(struct ntv_context *ctx, SpvId op, SpvId type, SpvId src0, SpvId src1, SpvId src2) in emit_atomic() argument
1714 src2, src1); in emit_atomic()
1717 emit_uint_const(ctx, 32, 0), src1); in emit_atomic()
1722 SpvId src0, SpvId src1) in emit_binop()
1724 return spirv_builder_emit_binop(&ctx->builder, op, type, src0, src1); in emit_binop()
1729 SpvId src0, SpvId src1, SpvId src2) in emit_triop()
1731 return spirv_builder_emit_triop(&ctx->builder, op, type, src0, src1, src2); in emit_triop()
1745 SpvId src0, SpvId src1) in emit_builtin_binop()
1721 emit_binop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src0, SpvId src1) emit_binop() argument
1728 emit_triop(struct ntv_context *ctx, SpvOp op, SpvId type, SpvId src0, SpvId src1, SpvId src2) emit_triop() argument
1744 emit_builtin_binop(struct ntv_context *ctx, enum GLSLstd450 op, SpvId type, SpvId src0, SpvId src1) emit_builtin_binop() argument
1753 emit_builtin_triop(struct ntv_context *ctx, enum GLSLstd450 op, SpvId type, SpvId src0, SpvId src1, SpvId src2) emit_builtin_triop() argument
2623 SpvId src1 = 0; emit_interpolate() local
[all...]
/third_party/mesa3d/src/amd/llvm/
H A Dac_nir_to_llvm.c151 LLVMValueRef src0, LLVMValueRef src1) in emit_int_cmp()
154 src1 = ac_to_integer(ctx, src1); in emit_int_cmp()
155 return LLVMBuildICmp(ctx->builder, pred, src0, src1, ""); in emit_int_cmp()
159 LLVMValueRef src0, LLVMValueRef src1) in emit_float_cmp()
162 src1 = ac_to_float(ctx, src1); in emit_float_cmp()
163 return LLVMBuildFCmp(ctx->builder, pred, src0, src1, ""); in emit_float_cmp()
209 LLVMValueRef src1) in emit_intrin_2f_param()
214 ac_to_float(ctx, src1), in emit_intrin_2f_param()
150 emit_int_cmp(struct ac_llvm_context *ctx, LLVMIntPredicate pred, LLVMValueRef src0, LLVMValueRef src1) emit_int_cmp() argument
158 emit_float_cmp(struct ac_llvm_context *ctx, LLVMRealPredicate pred, LLVMValueRef src0, LLVMValueRef src1) emit_float_cmp() argument
207 emit_intrin_2f_param(struct ac_llvm_context *ctx, const char *intrin, LLVMTypeRef result_type, LLVMValueRef src0, LLVMValueRef src1) emit_intrin_2f_param() argument
223 emit_intrin_3f_param(struct ac_llvm_context *ctx, const char *intrin, LLVMTypeRef result_type, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) emit_intrin_3f_param() argument
240 emit_bcsel(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2) emit_bcsel() argument
263 emit_uint_carry(struct ac_llvm_context *ctx, const char *intrin, LLVMValueRef src0, LLVMValueRef src1) emit_uint_carry() argument
374 emit_umul_high(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) emit_umul_high() argument
387 emit_imul_high(struct ac_llvm_context *ctx, LLVMValueRef src0, LLVMValueRef src1) emit_imul_high() argument
3185 LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]); visit_var_atomic() local
[all...]
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir.c516 nir_src *coord = NULL, *src1 = NULL, *src2 = NULL; in emit_tex() local
526 assert(!src1); in emit_tex()
527 src1 = &tex->src[i].src; in emit_tex()
541 src1 ? get_src(c, src1) : SRC_DISABLE, in emit_tex()
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc2196 const CPURegister& src1, in Emit()
2200 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); in Emit()
2203 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); in Emit()
2207 PushHelper(count, size, src0, src1, src2, src3); in Emit()
2251 const CPURegister& src1 = registers.PopLowestIndex(); in Emit() local
2252 if (src1.IsValid()) { in Emit()
2253 Stp(src0, src1, MemOperand(StackPointer(), offset)); in Emit()
2323 const CPURegister& src1, in Emit()
2332 VIXL_ASSERT(AreSameSizeAndType(src0, src1, src2, src3)); in Emit()
2339 VIXL_ASSERT(src1 in Emit()
2195 Push(const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) Emit() argument
2320 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) Emit() argument
[all...]
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.cc102 Condition cond, Register src1, in LoadRoot()
105 BranchShort(&skip, NegateCondition(cond), src1, src2); in LoadRoot()
3650 void TurboAssembler::MovToFloatParameters(DoubleRegister src1, in MovToFloatParameters() argument
3654 DCHECK(src1 != fparg2); in MovToFloatParameters()
3656 Move(fa0, src1); in MovToFloatParameters()
3658 Move(fa0, src1); in MovToFloatParameters()
4709 void TurboAssembler::FloatMinMaxHelper(FPURegister dst, FPURegister src1, in FloatMinMaxHelper() argument
4714 if (src1 == src2 && dst != src1) { in FloatMinMaxHelper()
4716 fmv_s(dst, src1); in FloatMinMaxHelper()
101 LoadRoot(Register destination, RootIndex index, Condition cond, Register src1, const Operand& src2) LoadRoot() argument
4764 Float32Max(FPURegister dst, FPURegister src1, FPURegister src2) Float32Max() argument
4770 Float32Min(FPURegister dst, FPURegister src1, FPURegister src2) Float32Min() argument
4776 Float64Max(FPURegister dst, FPURegister src1, FPURegister src2) Float64Max() argument
4782 Float64Min(FPURegister dst, FPURegister src1, FPURegister src2) Float64Min() argument
[all...]
/third_party/mesa3d/src/microsoft/compiler/
H A Ddxil_nir_lower_vs_vertex_conversion.c52 (*shift_right_func)(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1);
/third_party/ltp/tools/sparse/sparse-src/
H A Dir.c139 err += check_user(insn, insn->src1); in validate_insn()

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