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/kernel/linux/linux-6.6/arch/alpha/lib/
H A Dev6-stxncpy.S23 * t10 = bitmask (with one bit set) indicating the byte position of
25 * t12 = bitmask (with one bit set) indicating the last byte written
44 .set noat
45 .set noreorder
72 cmpbge zero, t2, t8 # E : bits set iff null found
106 the end-of-count bit is set in t8 iff it applies.
113 negq t8, t12 # E : find low bit set
223 of and we can set up to enter the main loop. */
296 negq t8, t6 # E : isolate low bit set
/kernel/linux/linux-6.6/arch/arm/kernel/
H A Dhead.S29 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
167 mov r8, r4 @ set TTBR1 to swapper_pg_dir
215 str r7, [r0], #4 @ set top PGD entry bits
216 str r3, [r0], #4 @ set bottom PGD entry bits
218 str r3, [r0], #4 @ set bottom PGD entry bits
219 str r7, [r0], #4 @ set top PGD entry bits
250 * set two variables to indicate the physical start and end of the
431 mcr p15, 0, ip, c2, c0, 0 @ set TTBR0
449 * processor setup function (or set in the case of r0)
/kernel/linux/linux-6.6/arch/arm/include/asm/
H A Dassembler.h76 * set to write-allocate (this would need further testing on XScale when WA
313 9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register
610 .set .Lpc\@, . + 8 // PC bias
624 .set .Lpc\@, . + (. - .Lb\@)
774 .set .Lrev_l_uses_tmp, 1
776 .set .Lrev_l_uses_tmp, 0
/kernel/linux/linux-5.10/drivers/net/ethernet/apple/
H A Dmacmace.c101 static void mace_load_rxdma_base(struct net_device *dev, int set) in mace_load_rxdma_base() argument
105 psc_write_word(PSC_ENETRD_CMD + set, 0x0100); in mace_load_rxdma_base()
106 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); in mace_load_rxdma_base()
107 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); in mace_load_rxdma_base()
108 psc_write_word(PSC_ENETRD_CMD + set, 0x9800); in mace_load_rxdma_base()
708 /* the other set, otherwise just reactivate this one. */ in mace_dma_intr()
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dinit.c12 u32 mask, set; in mt7915_mac_init_band() local
23 set = FIELD_PREP(MT_MDP_RCFR0_MCU_RX_MGMT, MT_MDP_TO_HIF) | in mt7915_mac_init_band()
26 mt76_rmw(dev, MT_MDP_BNRCFR0(band), mask, set); in mt7915_mac_init_band()
31 set = FIELD_PREP(MT_MDP_RCFR1_MCU_RX_BYPASS, MT_MDP_TO_HIF) | in mt7915_mac_init_band()
34 mt76_rmw(dev, MT_MDP_BNRCFR1(band), mask, set); in mt7915_mac_init_band()
140 * which should be set before firmware download stage. in mt7915_init_hardware()
/kernel/linux/linux-5.10/drivers/net/phy/
H A Dnxp-tja11xx.c93 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) in tja11xx_check() argument
97 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, in tja11xx_check()
102 u16 mask, u16 set) in phy_modify_check()
106 ret = phy_modify(phydev, reg, mask, set); in phy_modify_check()
110 return tja11xx_check(phydev, reg, mask, set); in phy_modify_check()
517 /* Overwrite parent device. phy_device_create() set parent to in tja1102_p1_register()
101 phy_modify_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) phy_modify_check() argument
/kernel/linux/linux-5.10/fs/overlayfs/
H A Doverlayfs.h407 bool set);
420 struct dentry *origin, bool set) in ovl_verify_origin()
423 false, set); in ovl_verify_origin()
427 struct dentry *upper, bool set) in ovl_verify_upper()
429 return ovl_verify_set_fh(ofs, index, OVL_XATTR_UPPER, upper, true, set); in ovl_verify_upper()
419 ovl_verify_origin(struct ovl_fs *ofs, struct dentry *upper, struct dentry *origin, bool set) ovl_verify_origin() argument
426 ovl_verify_upper(struct ovl_fs *ofs, struct dentry *index, struct dentry *upper, bool set) ovl_verify_upper() argument
/kernel/linux/linux-5.10/drivers/gpu/ipu-v3/
H A Dipu-di.c81 #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set)))
144 int set, int up, int down) in ipu_di_data_pin_config()
150 reg |= set << (di_pin * 2); in ipu_di_data_pin_config()
153 ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set)); in ipu_di_data_pin_config()
414 * the LDB clock has already been set correctly. in ipu_di_config_clock()
487 * based on the divider above. We want a 50% duty cycle, so set in ipu_di_config_clock()
592 /* set y_sel = 1 */ in ipu_di_init_sync_panel()
143 ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin, int set, int up, int down) ipu_di_data_pin_config() argument
/kernel/linux/linux-6.6/drivers/net/ethernet/apple/
H A Dmacmace.c101 static void mace_load_rxdma_base(struct net_device *dev, int set) in mace_load_rxdma_base() argument
105 psc_write_word(PSC_ENETRD_CMD + set, 0x0100); in mace_load_rxdma_base()
106 psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys); in mace_load_rxdma_base()
107 psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING); in mace_load_rxdma_base()
108 psc_write_word(PSC_ENETRD_CMD + set, 0x9800); in mace_load_rxdma_base()
712 /* the other set, otherwise just reactivate this one. */ in mace_dma_intr()
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-aspeed-sgpio.c288 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) in aspeed_sgpio_irq_set_mask() argument
301 if (set) in aspeed_sgpio_irq_set_mask()
307 if (set) in aspeed_sgpio_irq_set_mask()
317 if (!set) in aspeed_sgpio_irq_set_mask()
471 /* set falling or level-low irq */ in aspeed_sgpio_setup_irqs()
617 gpio->chip.set = aspeed_sgpio_set; in aspeed_sgpio_probe()
/kernel/linux/linux-6.6/drivers/net/phy/
H A Dnxp-tja11xx.c108 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) in tja11xx_check() argument
112 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set, in tja11xx_check()
117 u16 mask, u16 set) in phy_modify_check()
121 ret = phy_modify(phydev, reg, mask, set); in phy_modify_check()
125 return tja11xx_check(phydev, reg, mask, set); in phy_modify_check()
590 /* Overwrite parent device. phy_device_create() set parent to in tja1102_p1_register()
116 phy_modify_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set) phy_modify_check() argument
/kernel/linux/linux-6.6/drivers/gpu/ipu-v3/
H A Dipu-di.c81 #define DI_DW_SET(gen, set) (0x0088 + 4 * ((gen) + 0xc * (set)))
144 int set, int up, int down) in ipu_di_data_pin_config()
150 reg |= set << (di_pin * 2); in ipu_di_data_pin_config()
153 ipu_di_write(di, (down << 16) | up, DI_DW_SET(wave_gen, set)); in ipu_di_data_pin_config()
410 * the LDB clock has already been set correctly. in ipu_di_config_clock()
483 * based on the divider above. We want a 50% duty cycle, so set in ipu_di_config_clock()
595 /* set y_sel = 1 */ in ipu_di_init_sync_panel()
143 ipu_di_data_pin_config(struct ipu_di *di, int wave_gen, int di_pin, int set, int up, int down) ipu_di_data_pin_config() argument
/kernel/linux/linux-6.6/security/selinux/ss/
H A Davtab.c383 unsigned int set, vers = pol->policyvers; in avtab_read_item() local
480 set = 0; in avtab_read_item()
483 set++; in avtab_read_item()
485 if (!set || set > 1) { in avtab_read_item()
/kernel/linux/linux-6.6/net/devlink/
H A Dparam.c163 if (!param->set) in devlink_param_set()
165 return param->set(devlink, param->id, ctx); in devlink_param_set()
571 if (!param->set) in __devlink_nl_cmd_param_set_doit()
633 WARN_ON(param->get || param->set); in devlink_param_register()
635 WARN_ON(!param->get || !param->set); in devlink_param_register()
795 * devl_param_driverinit_value_set - set value of configuration
801 * @init_val: value of parameter to set for driverinit configuration mode
803 * This function should be used by the driver to set driverinit
/third_party/ffmpeg/libavfilter/x86/
H A Dvf_blend.asm84 ; %1 name , %2 src (b or w), %3 inter (w or d), %4 (1 if 16bit, not set if 8 bit)
184 ;%1 name, %2 (b or w), %3 (set if 16 bit)
205 ; %1 name , %2 src (b or w), %3 inter (w or d), %4 (1 if 16bit, not set if 8 bit)
313 ; %1 name , %2 src (b or w), %3 inter (w or d), %4 (1 if 16bit, not set if 8 bit)
342 ; %1 name , %2 src (b or w), %3 inter (w or d), %4 (1 if 16bit, not set if 8 bit)
/third_party/icu/icu4c/source/common/
H A Ducnv_ct.cpp482 /* set up the subconverter arguments */ in UConverter_toUnicode_CompoundText_OFFSETS()
593 sa->add(sa->set, 0x0000); in _CompoundText_GetUnicodeSet()
594 sa->add(sa->set, 0x0009); in _CompoundText_GetUnicodeSet()
595 sa->add(sa->set, 0x000A); in _CompoundText_GetUnicodeSet()
596 sa->addRange(sa->set, 0x0020, 0x007F); in _CompoundText_GetUnicodeSet()
597 sa->addRange(sa->set, 0x00A0, 0x00FF); in _CompoundText_GetUnicodeSet()
/third_party/node/lib/internal/console/
H A Dconstructor.js153 optionsMap.set(this, inspectOptions);
218 set(value) { stdout = value; },
228 set(value) { stderr = value; },
405 this._times.set(label, process.hrtime());
469 counts.set(label, count);
/third_party/node/deps/v8/third_party/jinja2/
H A Dext.py70 tags = set()
282 referenced = set()
442 tags = set(["do"])
453 tags = set(["break", "continue"])
519 If you don't want that behavior set the `babel_style` parameter to `False`
624 is now set to a list of keywords for extraction, the extractor will
631 The `newstyle_gettext` flag can be set to `True` to enable newstyle
635 A `silent` option can now be provided. If set to `False` template
647 extensions = set()
/third_party/node/test/fixtures/wpt/resources/
H A Dchannel.sub.js74 this.readSockets.set(uuid, socket);
78 throw new Error("Can't set message handler for write sockets");
89 this.writeSockets.set(uuid, [socket, count]);
110 target.set(uuid, [socket, count]);
481 this.responseHandlers.set(commandId, fn);
509 * its URL set to the same as the ``uuid`` property of this
694 remoteObjectsById.set(rv, obj);
859 case "set":
883 objectsSeen.set(item, serialized);
894 case "set"
[all...]
/third_party/nghttp2/src/
H A Dshrpx_worker_process.cc602 sigset_t set; in worker_process_event_loop() local
603 sigemptyset(&set); in worker_process_event_loop()
604 sigaddset(&set, SIGCHLD); in worker_process_event_loop()
606 rv = pthread_sigmask(SIG_BLOCK, &set, nullptr); in worker_process_event_loop()
620 rv = pthread_sigmask(SIG_UNBLOCK, &set, nullptr); in worker_process_event_loop()
/third_party/node/deps/icu-small/source/common/
H A Ducnv_ct.cpp482 /* set up the subconverter arguments */ in UConverter_toUnicode_CompoundText_OFFSETS()
593 sa->add(sa->set, 0x0000); in _CompoundText_GetUnicodeSet()
594 sa->add(sa->set, 0x0009); in _CompoundText_GetUnicodeSet()
595 sa->add(sa->set, 0x000A); in _CompoundText_GetUnicodeSet()
596 sa->addRange(sa->set, 0x0020, 0x007F); in _CompoundText_GetUnicodeSet()
597 sa->addRange(sa->set, 0x00A0, 0x00FF); in _CompoundText_GetUnicodeSet()
/third_party/mesa3d/src/intel/genxml/
H A Dgen_pack_header.py564 self.enums = set()
585 self.instruction_engines = set(attrs["engine"].split('|'))
764 if set(engines) - set(valid_engines):
771 p.engines = set(engines)
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_ssa.cpp248 usedBeforeAssigned.set(i->getSrc(s)->id); in buildLiveSetsPreSSA()
250 assigned.set(i->getDef(d)->id); in buildLiveSetsPreSSA()
257 usedBeforeAssigned.set(it->get()->id); in buildLiveSetsPreSSA()
282 bb->defSet.set(i->getDef(d)->id); in buildDefSetsPreSSA()
539 it->set(lval); in search()
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-graph-printer.cc119 const std::set<size_t>& arrows_starting_here = {}, in PrintVerticalArrows()
120 const std::set<BasicBlock*>& targets_starting_here = {},
166 std::set<size_t>* arrows_starting_here = nullptr) { in AddTargetIfNotNext()
452 std::set<size_t> arrows_starting_here; in Process()
465 std::set<size_t> arrows_starting_here; in Process()
/third_party/skia/samplecode/
H A DSamplePatch.cpp100 pt->set(x, y); in eval_sheet()
173 tex[i*2 + 0].set(s, t); in draw()
174 tex[i*2 + 1].set(s, t + dt); in draw()
230 fSize1.set(2, 2);
311 fPts[((PtClick*)click)->fIndex].set(click->fCurr.fX - DX, click->fCurr.fY - DY);

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