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/third_party/mesa3d/src/gallium/drivers/r600/
H A Devergreen_compute.h45 struct r600_resource* r600_compute_buffer_alloc_vram(struct r600_screen *screen, unsigned size);
46 struct pipe_resource *r600_compute_global_buffer_create(struct pipe_screen *screen, const struct pipe_resource *templ);
47 void r600_compute_global_buffer_destroy(struct pipe_screen *screen,
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_state.c477 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_load_register_reg32()
486 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_load_register_reg64()
495 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_load_register_imm32()
504 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_load_register_imm64()
517 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_load_register_mem32()
533 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_load_register_mem64()
546 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_store_register_mem32()
563 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_store_register_mem64()
580 mi_builder_init(&b, &batch->screen->devinfo, batch); in iris_store_data_imm32()
594 mi_builder_init(&b, &batch->screen in iris_store_data_imm64()
1632 UNUSED struct iris_screen *screen = (void *) ice->ctx.screen; want_pma_fix() local
2153 UNUSED struct iris_screen *screen = (void *)ctx->screen; iris_create_sampler_state() local
2223 struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen; iris_upload_sampler_states() local
2535 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_create_sampler_view() local
2654 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_create_surface() local
2858 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_set_shader_images() local
2976 UNUSED struct iris_screen *screen = (void *) ctx->screen; iris_set_sampler_views() local
3244 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_set_framebuffer_state() local
3599 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_set_vertex_buffers() local
3695 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_create_vertex_elements() local
3872 struct iris_screen *screen = (struct iris_screen *)ctx->screen; iris_set_stream_output_targets() local
4424 struct iris_screen *screen = (void *) ice->ctx.screen; iris_populate_fs_key() local
5559 struct iris_screen *screen = batch->screen; invalidate_aux_map_state() local
5590 struct iris_screen *screen = batch->screen; init_aux_map_state() local
5801 struct iris_screen *screen = batch->screen; iris_upload_dirty_render_state() local
7124 struct iris_screen *screen = batch->screen; iris_upload_compute_walker() local
7189 struct iris_screen *screen = batch->screen; iris_upload_gpgpu_walker() local
7340 struct iris_screen *screen = batch->screen; iris_upload_compute_state() local
8406 init_screen_state(struct iris_screen *screen) init_screen_state() argument
8446 struct iris_screen *screen = (struct iris_screen *)ctx->screen; init_state() local
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H A Diris_measure.h36 void iris_init_screen_measure(struct iris_screen *screen);
41 void iris_destroy_screen_measure(struct iris_screen *screen);
52 if (unlikely(((struct iris_screen *) ice->ctx.screen)->measure.config)) \
H A Diris_batch.h65 struct iris_screen *screen; member
298 iris_syncobj_reference(batch->screen->bufmgr, out_syncobj, syncobj); in iris_batch_reference_signal_syncobj()
348 batch->next_seqno = p_atomic_inc_return(&batch->screen->last_seqno); in iris_batch_sync_boundary()
361 const struct intel_device_info *devinfo = &batch->screen->devinfo; in iris_batch_mark_flush_sync()
378 const struct intel_device_info *devinfo = &batch->screen->devinfo; in iris_batch_mark_invalidate_sync()
432 batch <= &ice->batches[((struct iris_screen *)ice->ctx.screen)->devinfo.ver >= 12 ? IRIS_BATCH_BLITTER : IRIS_BATCH_COMPUTE]; \
H A Diris_pipe_control.c80 batch->screen->vtbl.emit_raw_pipe_control(batch, reason, flags, NULL, 0, 0); in iris_emit_pipe_control_flush()
97 batch->screen->vtbl.emit_raw_pipe_control(batch, reason, flags, bo, offset, imm); in iris_emit_pipe_control_write()
151 batch->screen->workaround_address.bo, in iris_emit_end_of_pipe_sync()
152 batch->screen->workaround_address.offset, 0); in iris_emit_end_of_pipe_sync()
187 const struct intel_device_info *devinfo = &batch->screen->devinfo; in iris_emit_buffer_barrier_for()
188 const struct brw_compiler *compiler = batch->screen->compiler; in iris_emit_buffer_barrier_for()
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_texture_state.c90 struct etna_screen *screen = ctx->screen; in etna_create_sampler_state_state() local
113 cs->config1 = screen->specs.seamless_cube_map ? in etna_create_sampler_state_state()
143 if ((ctx->screen->specs.halti < 2) && ss->compare_mode) { in etna_create_sampler_state_state()
167 struct etna_screen *screen = ctx->screen; in etna_create_sampler_view_state() local
265 if (!screen->specs.npot_tex_any_wrap && in etna_create_sampler_view_state()
339 struct etna_screen *screen = ctx->screen; in etna_emit_new_texture_state() local
435 if (unlikely(screen in etna_emit_new_texture_state()
471 struct etna_screen *screen = ctx->screen; etna_emit_texture_state() local
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/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_simulator.c34 * appears on the screen as if actual hardware rendering had been done.
87 * calling us for BO allocation can get to our screen.
232 struct vc4_screen *screen = dev->screen; in drm_gem_cma_create() local
233 struct vc4_simulator_bo *sim_bo = vc4_create_simulator_bo(screen->fd, in drm_gem_cma_create()
669 vc4_simulator_init(struct vc4_screen *screen) in vc4_simulator_init() argument
673 screen->sim_file = rzalloc(screen, struct vc4_simulator_file); in vc4_simulator_init()
675 screen->sim_file->bo_map = in vc4_simulator_init()
676 _mesa_hash_table_create(screen in vc4_simulator_init()
689 vc4_simulator_destroy(struct vc4_screen *screen) vc4_simulator_destroy() argument
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H A Dvc4_resource.c45 struct pipe_screen *pscreen = prsc->screen; in vc4_resource_bo_alloc()
263 struct vc4_screen *screen = vc4_screen(pscreen); in vc4_resource_destroy() local
268 renderonly_scanout_destroy(rsc->scanout, screen->ro); in vc4_resource_destroy()
289 struct vc4_screen *screen = vc4_screen(pscreen); in vc4_resource_get_handle() local
304 if (screen->ro) { in vc4_resource_get_handle()
314 if (screen->ro) { in vc4_resource_get_handle()
464 prsc->screen = pscreen; in vc4_resource_setup()
502 struct vc4_screen *screen = vc4_screen(pscreen); in vc4_resource_create_with_modifiers() local
518 if (screen->ro && (tmpl->bind & PIPE_BIND_SCANOUT)) in vc4_resource_create_with_modifiers()
538 PIPE_BIND_SCANOUT)) && !screen in vc4_resource_create_with_modifiers()
619 struct vc4_screen *screen = vc4_screen(pscreen); vc4_resource_from_handle() local
1131 struct vc4_screen *screen = vc4_screen(pscreen); vc4_resource_screen_init() local
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/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
H A Dnvc0_vbo.c261 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size); in nvc0_update_user_vbufs()
303 NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size); in nvc0_update_user_vbufs_shared()
365 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS) in nvc0_validate_vertex_buffers()
415 if (nvc0->screen->eng3d->oclass < TU102_3D_CLASS) in nvc0_validate_vertex_buffers_shared()
562 struct nvc0_screen *screen = push->user_priv; in nvc0_draw_vbo_kick_notify() local
564 nouveau_fence_update(&screen->base, true); in nvc0_draw_vbo_kick_notify()
566 NOUVEAU_DRV_STAT(&screen->base, pushbuf_count, 1); in nvc0_draw_vbo_kick_notify()
599 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_array, 1); in nvc0_draw_arrays()
765 NOUVEAU_DRV_STAT(&nvc0->screen->base, draw_calls_indexed, 1); in nvc0_draw_elements()
784 if (nvc0->screen in nvc0_draw_stream_output()
816 struct nvc0_screen *screen = nvc0->screen; nvc0_draw_indirect() local
943 struct nvc0_screen *screen = nvc0->screen; nvc0_draw_vbo() local
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/third_party/mesa3d/src/glx/
H A Dglxext.c240 ** Free the per screen configs data as well as the array of
249 /* Free screen configuration information */ in FreeScreenConfigs()
292 /* Needs to be done before free screen. */ in glx_display_free()
648 int screen, GLboolean tagged_only) in createConfigsFromProperties()
690 m->screen = screen; in createConfigsFromProperties()
702 struct glx_display *priv, int screen) in getVisualConfigs()
714 req->screen = screen; in getVisualConfigs()
722 screen, GL_FALS in getVisualConfigs()
647 createConfigsFromProperties(Display * dpy, int nvisuals, int nprops, int screen, GLboolean tagged_only) createConfigsFromProperties() argument
701 getVisualConfigs(struct glx_screen *psc, struct glx_display *priv, int screen) getVisualConfigs() argument
730 getFBConfigs(struct glx_screen *psc, struct glx_display *priv, int screen) getFBConfigs() argument
780 glx_screen_init(struct glx_screen *psc, int screen, struct glx_display * priv) glx_screen_init() argument
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/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_get.c513 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir, in si_get_compiler_options() argument
516 struct si_screen *sscreen = (struct si_screen *)screen; in si_get_compiler_options()
541 static int si_get_video_param_no_video_hw(struct pipe_screen *screen, enum pipe_video_profile profile, in si_get_video_param_no_video_hw() argument
547 return vl_profile_supported(screen, profile, entrypoint); in si_get_video_param_no_video_hw()
552 return vl_video_buffer_max_size(screen); in si_get_video_param_no_video_hw()
562 return vl_level_supported(screen, profile); in si_get_video_param_no_video_hw()
568 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile, in si_get_video_param() argument
571 struct si_screen *sscreen = (struct si_screen *)screen; in si_get_video_param()
782 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format, in si_vid_is_format_supported() argument
799 return vl_video_buffer_is_format_supported(screen, forma in si_vid_is_format_supported()
802 get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type) get_max_threads_per_block() argument
811 si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type, enum pipe_compute_cap param, void *ret) si_get_compute_param() argument
960 si_get_timestamp(struct pipe_screen *screen) si_get_timestamp() argument
968 si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info) si_query_memory_info() argument
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H A Dsi_state_streamout.c114 if (sctx->screen->use_ngg_streamout) { in si_set_streamout_targets()
162 unsigned buf_filled_size_size = sctx->screen->use_ngg_streamout ? 8 : 4; in si_set_streamout_targets()
194 if (sctx->screen->use_ngg_streamout) { in si_set_streamout_targets()
256 if (!sctx->screen->use_ngg_streamout) in si_emit_streamout_begin()
265 if (sctx->screen->use_ngg_streamout) { in si_emit_streamout_begin()
333 if (!sctx->screen->use_ngg_streamout) in si_emit_streamout_end()
342 if (sctx->screen->use_ngg_streamout) { in si_emit_streamout_end()
383 assert(!sctx->screen->use_ngg_streamout); in si_emit_streamout_enable()
407 if (!sctx->screen->use_ngg_streamout && in si_set_streamout_enable()
415 if (!sctx->screen in si_update_prims_generated_query_state()
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H A Dsi_gfx_cs.c38 struct si_screen *sscreen = ctx->screen; in si_flush_gfx_cs()
193 si_resource(pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 4)); in si_begin_gfx_cs_debug()
212 if (sctx->screen->gds) { in si_add_gds_to_buffer_list()
213 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->screen->gds, RADEON_USAGE_READWRITE, 0); in si_add_gds_to_buffer_list()
214 if (sctx->screen->gds_oa) { in si_add_gds_to_buffer_list()
215 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->screen->gds_oa, RADEON_USAGE_READWRITE, 0); in si_add_gds_to_buffer_list()
224 if (sctx->screen->gds && sctx->screen->gds_oa) in si_allocate_gds()
227 assert(sctx->screen->use_ngg_streamout); in si_allocate_gds()
230 simple_mtx_lock(&sctx->screen in si_allocate_gds()
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H A Dsi_cp_reg_shadowing.c80 if (sctx->screen->dpbb_allowed) { in si_create_shadowing_ib_preamble()
178 si_build_load_reg(sctx->screen, pm4, i, sctx->shadowed_regs); in si_create_shadowing_ib_preamble()
194 if (sctx->screen->info.mid_command_buffer_preemption_enabled || in si_init_cp_reg_shadowing()
195 sctx->screen->debug_flags & DBG(SHADOW_REGS)) { in si_init_cp_reg_shadowing()
197 si_aligned_buffer_create(sctx->b.screen, in si_init_cp_reg_shadowing()
222 ac_emulate_clear_state(&sctx->screen->info, &sctx->gfx_cs, si_set_context_reg_array); in si_init_cp_reg_shadowing()
/third_party/mesa3d/src/gallium/frontends/vdpau/
H A Dsurface.c86 p_surf->templat.buffer_format = pipe->screen->get_video_param in vlVdpVideoSurfaceCreate()
88 pipe->screen, in vlVdpVideoSurfaceCreate()
95 p_surf->templat.interlaced = pipe->screen->get_video_param in vlVdpVideoSurfaceCreate()
97 pipe->screen, in vlVdpVideoSurfaceCreate()
329 struct pipe_screen *screen = pipe->screen; in vlVdpVideoSurfacePutBitsYCbCr() local
332 if (!screen->is_video_format_supported(screen, nformat, in vlVdpVideoSurfacePutBitsYCbCr()
335 nformat = screen->get_video_param(screen, in vlVdpVideoSurfacePutBitsYCbCr()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
H A Dnv98_video.c89 struct nouveau_screen *screen = &nv50->screen->base; in nv98_create_decoder() local
118 ret = nouveau_object_new(&screen->device->object, 0, in nv98_create_decoder()
187 ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, in nv98_create_decoder()
190 ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, in nv98_create_decoder()
227 ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0, in nv98_create_decoder()
232 ret = nouveau_vp3_load_firmware(dec, templ->profile, screen->device->chipset); in nv98_create_decoder()
237 ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0, in nv98_create_decoder()
244 ret = nouveau_bo_new(screen->device, NOUVEAU_BO_VRAM, 0, in nv98_create_decoder()
267 ret = nouveau_bo_new(screen in nv98_create_decoder()
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/third_party/mesa3d/src/gallium/frontends/hgl/
H A Dhgl_context.h41 struct pipe_screen* screen; member
90 struct st_manager* hgl_create_st_manager(struct hgl_context* screen);
98 struct hgl_display* hgl_create_display(struct pipe_screen* screen);
/third_party/libdrm/tests/tegra/
H A Ddrm-test.h58 int drm_screen_close(struct drm_screen *screen);
59 int drm_screen_set_framebuffer(struct drm_screen *screen,
63 struct drm_screen *screen, uint32_t handle,
/third_party/mesa3d/src/gallium/auxiliary/driver_rbug/
H A Drbug_screen.h42 struct pipe_screen *screen; member
60 rbug_screen(struct pipe_screen *screen) in rbug_screen() argument
62 return (struct rbug_screen *)screen; in rbug_screen()
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_fine_fence.h82 void crocus_fine_fence_destroy(struct crocus_screen *screen,
86 crocus_fine_fence_reference(struct crocus_screen *screen, in crocus_fine_fence_reference() argument
91 crocus_fine_fence_destroy(screen, *dst); in crocus_fine_fence_reference()
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_state.c287 struct svga_screen *screen = svga_screen(svga->pipe.screen); in svga_update_state() local
291 SVGA_STATS_TIME_PUSH(screen->sws, SVGA_STATS_TIME_UPDATESTATE); in svga_update_state()
297 if (svga->state.texture_timestamp != screen->texture_timestamp) { in svga_update_state()
298 svga->state.texture_timestamp = screen->texture_timestamp; in svga_update_state()
324 SVGA_STATS_TIME_POP(screen->sws); in svga_update_state()
H A Dsvga_swtnl_draw.c159 struct svga_screen *screen = svga_screen(svga->pipe.screen); in svga_init_swtnl() local
185 if (!screen->haveLineSmooth) in svga_init_swtnl()
189 draw_enable_line_stipple(svga->swtnl.draw, !screen->haveLineStipple); in svga_init_swtnl()
197 MAX2(screen->maxLineWidth, in svga_init_swtnl()
198 screen->maxLineWidthAA)); in svga_init_swtnl()
/third_party/mesa3d/src/gallium/winsys/svga/drm/
H A Dvmw_surface.c46 struct vmw_winsys_screen *vws = vsrf->screen; in vmw_svga_winsys_surface_init()
95 vmw_svga_winsys_buffer_unmap(&vsrf->screen->base, vsrf->buf); in vmw_svga_winsys_surface_init()
112 struct vmw_winsys_screen *vws = vsrf->screen; in vmw_svga_winsys_surface_map()
241 vmw_svga_winsys_buffer_unmap(&vsrf->screen->base, vsrf->buf); in vmw_svga_winsys_surface_unmap()
263 vmw_svga_winsys_buffer_destroy(&dst->screen->base, dst->buf); in vmw_svga_winsys_surface_reference()
264 vmw_ioctl_surface_destroy(dst->screen, dst->sid); in vmw_svga_winsys_surface_reference()
/third_party/mesa3d/src/gallium/drivers/freedreno/
H A Dfreedreno_fence.c110 drmSyncobjDestroy(fd_device_fd(fence->screen->dev), fence->syncobj); in fd_fence_destroy()
177 fence->screen = ctx->screen; in fence_create()
200 assert(ctx->screen->has_syncobj); in fd_create_fence_fd()
201 ret = drmSyncobjFDToHandle(fd_device_fd(ctx->screen->dev), fd, &syncobj); in fd_create_fence_fd()
244 drmSyncobjSignal(fd_device_fd(ctx->screen->dev), &fence->syncobj, 1); in fd_fence_server_signal()
/third_party/mesa3d/src/gallium/auxiliary/util/
H A Du_upload_mgr.c76 pipe->screen->get_param(pipe->screen, in u_upload_create()
180 struct pipe_screen *screen = upload->pipe->screen; in u_upload_alloc_buffer() local
208 upload->buffer = screen->resource_create(screen, &buffer); in u_upload_alloc_buffer()

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