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/third_party/libunwind/libunwind/src/arm/
H A DGregs.c28 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp, in tdep_access_reg() argument
33 switch (reg) in tdep_access_reg()
66 loc = c->dwarf.loc[reg - UNW_ARM_R0]; in tdep_access_reg()
80 Debug (1, "bad register number %u\n", reg); in tdep_access_reg()
93 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp, in tdep_access_fpreg() argument
96 Debug (1, "bad register number %u\n", reg); in tdep_access_fpreg()
/third_party/libunwind/libunwind/src/sh/
H A DGregs.c29 tdep_access_reg (struct cursor *c, unw_regnum_t reg, unw_word_t *valp, in tdep_access_reg() argument
34 switch (reg) in tdep_access_reg()
55 loc = c->dwarf.loc[reg]; in tdep_access_reg()
65 Debug (1, "bad register number %u\n", reg); in tdep_access_reg()
76 tdep_access_fpreg (struct cursor *c, unw_regnum_t reg, unw_fpreg_t *valp, in tdep_access_fpreg() argument
79 Debug (1, "bad register number %u\n", reg); in tdep_access_fpreg()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_soa.c695 "load addr reg"); in get_indirect_index()
700 rel = LLVMBuildLoad(builder, rel, "load temp reg"); in get_indirect_index()
804 const struct tgsi_full_src_register * reg, in emit_fetch_constant()
821 if (reg->Register.Dimension) { in emit_fetch_constant()
822 assert(!reg->Dimension.Indirect); in emit_fetch_constant()
823 dimension = reg->Dimension.Index; in emit_fetch_constant()
830 if (reg->Register.Indirect) { in emit_fetch_constant()
839 reg->Register.File, in emit_fetch_constant()
840 reg->Register.Index, in emit_fetch_constant()
841 &reg in emit_fetch_constant()
802 emit_fetch_constant( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_constant() argument
954 emit_fetch_immediate( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_immediate() argument
1034 emit_fetch_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_input() argument
1115 emit_fetch_gs_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_gs_input() argument
1203 emit_fetch_tcs_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_tcs_input() argument
1306 emit_fetch_tes_input( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_tes_input() argument
1402 emit_fetch_temporary( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_temporary() argument
1471 emit_fetch_system_value( struct lp_build_tgsi_context * bld_base, const struct tgsi_full_src_register * reg, enum tgsi_opcode_type stype, unsigned swizzle_in) emit_fetch_system_value() argument
1676 emit_store_output(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type dtype, const struct tgsi_full_dst_register *reg, unsigned index, unsigned chan_index, LLVMValueRef indirect_index, LLVMValueRef value) emit_store_output() argument
1725 emit_store_tcs_output(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type dtype, const struct tgsi_full_dst_register *reg, unsigned index, unsigned chan_index, LLVMValueRef indirect_index, LLVMValueRef value) emit_store_tcs_output() argument
1784 emit_store_temp(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type dtype, const struct tgsi_full_dst_register *reg, unsigned index, unsigned chan_index, LLVMValueRef indirect_index, LLVMValueRef value) emit_store_temp() argument
1837 emit_store_address(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type dtype, const struct tgsi_full_dst_register *reg, unsigned index, unsigned chan_index, LLVMValueRef indirect_index, LLVMValueRef value) emit_store_address() argument
1871 const struct tgsi_full_dst_register *reg = &inst->Dst[index]; emit_store_chan() local
2017 const struct tgsi_full_src_register *reg = &inst->Src[src_op]; lp_build_lod_property() local
2726 const struct tgsi_full_src_register *reg = &inst->Src[0]; emit_kill_if() local
2850 struct tgsi_full_src_register reg; emit_dump_file() local
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/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/
H A Dregalloc.c67 BITSET_CLEAR(live, store->reg->index); in propagate_liveness_node()
75 BITSET_SET(live, load->reg->index); in propagate_liveness_node()
108 BITSET_SET(block->def_out, store->reg->index); in calc_def_block()
190 printf("reg%d ", live_idx); in print_liveness()
223 add_all_interferences(ctx, store->reg->index, ctx->live); in calc_interference()
226 BITSET_CLEAR(ctx->live, store->reg->index); in calc_interference()
230 BITSET_SET(ctx->live, load->reg->index); in calc_interference()
247 gpir_debug("pushing reg%u\n", i); in push_stack()
291 for (int reg = 0; reg < ct in do_regalloc()
311 struct reg_info *reg = &ctx->registers[idx]; do_regalloc() local
401 unsigned reg = UINT_MAX; find_free_value_reg() local
447 unsigned reg = find_free_value_reg(ctx); handle_value_read() local
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/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Ddisasm.c62 print_reg(ppir_codegen_vec4_reg reg, const char *special, FILE *fp) in print_reg() argument
67 switch (reg) in print_reg()
82 fprintf(fp, "$%u", reg); in print_reg()
89 print_vector_source(ppir_codegen_vec4_reg reg, const char *special, in print_vector_source() argument
97 print_reg(reg, special, fp); in print_vector_source()
105 print_source_scalar(unsigned reg, const char *special, bool abs, bool neg, FILE *fp) in print_source_scalar() argument
112 print_reg(reg >> 2, special, fp); in print_source_scalar()
114 fprintf(fp, ".%c", "xyzw"[reg & 3]); in print_source_scalar()
139 unsigned reg = (varying->imm.offset_vector << 2) + in print_varying_source() local
142 print_source_scalar(reg, NUL in print_varying_source()
166 print_dest_scalar(unsigned reg, FILE *fp) print_dest_scalar() argument
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/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir2_nir.c209 update_range(struct ir2_context *ctx, struct ir2_reg *reg) in update_range() argument
211 if (!reg->initialized) { in update_range()
212 reg->initialized = true; in update_range()
213 reg->loop_depth = ctx->loop_depth; in update_range()
216 if (ctx->loop_depth > reg->loop_depth) { in update_range()
217 reg->block_idx_free = ctx->loop_last_block[reg->loop_depth + 1]; in update_range()
219 reg->loop_depth = ctx->loop_depth; in update_range()
220 reg->block_idx_free = -1; in update_range()
226 if (reg in update_range()
234 struct ir2_reg *reg; make_src() local
263 struct ir2_reg *reg = &instr->ssa; set_index() local
355 struct ir2_reg *reg; instr_create_alu_reg() local
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/drivers/peripheral/sensor/chipset/als/
H A Dals_bh1745.c186 uint8_t reg[ALS_LIGHT_BUTT]; in ReadBh1745RawData() local
190 (void)memset_s(reg, sizeof(reg), 0, sizeof(reg)); in ReadBh1745RawData()
206 ret = ReadSensor(&data->busCfg, BH1745_ALS_R_LSB_ADDR, &reg[ALS_R_LSB], sizeof(uint8_t)); in ReadBh1745RawData()
209 ret = ReadSensor(&data->busCfg, BH1745_ALS_R_MSB_ADDR, &reg[ALS_R_MSB], sizeof(uint8_t)); in ReadBh1745RawData()
212 ret = ReadSensor(&data->busCfg, BH1745_ALS_G_LSB_ADDR, &reg[ALS_G_LSB], sizeof(uint8_t)); in ReadBh1745RawData()
215 ret = ReadSensor(&data->busCfg, BH1745_ALS_G_MSB_ADDR, &reg[ALS_G_MSB], sizeof(uint8_t)); in ReadBh1745RawData()
218 ret = ReadSensor(&data->busCfg, BH1745_ALS_B_LSB_ADDR, &reg[ALS_B_LSB], sizeof(uint8_t)); in ReadBh1745RawData()
221 ret = ReadSensor(&data->busCfg, BH1745_ALS_B_MSB_ADDR, &reg[ALS_B_MS in ReadBh1745RawData()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/
H A Dnvfx_vertprog.c128 switch (src.reg.type) { in emit_src()
131 sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT)); in emit_src()
136 vp->ir |= (1 << src.reg.index); in emit_src()
137 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT)); in emit_src()
142 if (src.reg.index < 256 && src.reg.index >= -256) { in emit_src()
144 reloc.target = src.reg.index; in emit_src()
147 hw[1] |= (src.reg.index << NVFX_VP(INST_CONST_SRC_SHIFT)) & in emit_src()
171 if(src.reg.type == NVFXSR_CONST) in emit_src()
173 else if(src.reg in emit_src()
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/third_party/mesa3d/src/compiler/nir/
H A Dnir.c236 nir_register *reg = ralloc(mem_ctx, nir_register); in reg_create() local
238 list_inithead(&reg->uses); in reg_create()
239 list_inithead(&reg->defs); in reg_create()
240 list_inithead(&reg->if_uses); in reg_create()
242 reg->num_components = 0; in reg_create()
243 reg->bit_size = 32; in reg_create()
244 reg->num_array_elems = 0; in reg_create()
245 reg->divergent = false; in reg_create()
247 exec_list_push_tail(list, &reg->node); in reg_create()
249 return reg; in reg_create()
255 nir_register *reg = reg_create(ralloc_parent(impl), &impl->registers); nir_local_reg_create() local
262 nir_reg_remove(nir_register *reg) nir_reg_remove() argument
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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_eu_emit.c71 gfx7_convert_mrf_to_grf(struct brw_codegen *p, struct brw_reg *reg) in gfx7_convert_mrf_to_grf() argument
82 if (devinfo->ver >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) { in gfx7_convert_mrf_to_grf()
83 reg->file = BRW_GENERAL_REGISTER_FILE; in gfx7_convert_mrf_to_grf()
84 reg->nr += GFX7_MRF_HACK_START; in gfx7_convert_mrf_to_grf()
209 brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) in brw_set_src0() argument
213 if (reg.file == BRW_MESSAGE_REGISTER_FILE) in brw_set_src0()
214 assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->ver)); in brw_set_src0()
215 else if (reg.file == BRW_GENERAL_REGISTER_FILE) in brw_set_src0()
216 assert(reg.nr < 128); in brw_set_src0()
218 gfx7_convert_mrf_to_grf(p, &reg); in brw_set_src0()
345 brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg) brw_set_src1() argument
755 get_3src_subreg_nr(struct brw_reg reg) get_3src_subreg_nr() argument
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H A Dbrw_shader.cpp569 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg) in brw_saturate_immediate() argument
585 imm.ud = reg->ud; in brw_saturate_immediate()
587 imm.df = reg->df; in brw_saturate_immediate()
619 reg->ud = sat_imm.ud; in brw_saturate_immediate()
624 reg->df = sat_imm.df; in brw_saturate_immediate()
632 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg) in brw_negate_immediate() argument
637 reg->d = -reg->d; in brw_negate_immediate()
641 uint16_t value = -(int16_t)reg->ud; in brw_negate_immediate()
642 reg in brw_negate_immediate()
675 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg) brw_abs_immediate() argument
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/third_party/backends/backend/
H A Drts88xx_lib.c127 sanei_rts88xx_read_reg (SANE_Int devnum, SANE_Int index, SANE_Byte * reg) in sanei_rts88xx_read_reg() argument
143 status = sanei_usb_read_bulk (devnum, reg, &size); in sanei_rts88xx_read_reg()
149 DBG (DBG_io2, "sanei_rts88xx_read_reg: reg[0x%02x]=0x%02x\n", index, *reg); in sanei_rts88xx_read_reg()
157 sanei_rts88xx_write_reg (SANE_Int devnum, SANE_Int index, SANE_Byte * reg) in sanei_rts88xx_write_reg() argument
164 cmd[4] = *reg; in sanei_rts88xx_write_reg()
173 DBG (DBG_io2, "sanei_rts88xx_write_reg: reg[0x%02x]=0x%02x\n", index, *reg); in sanei_rts88xx_write_reg()
344 SANE_Byte reg; in sanei_rts88xx_reset_lamp() local
347 status = sanei_rts88xx_read_reg (devnum, 0xda, &reg); in sanei_rts88xx_reset_lamp()
648 SANE_Byte local[2], reg; sanei_rts88xx_setup_nvram() local
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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_postsched.c421 * The 'reg' arg is really just to know half vs full precision.
430 struct ir3_postsched_node *node, const struct ir3_register *reg, in add_reg_dep()
438 if ((reg->flags & IR3_REG_HALF) && !is_reg_special(reg)) { in add_reg_dep()
439 /* single conflict in half-reg space: */ in add_reg_dep()
442 /* two conflicts in half-reg space: */ in add_reg_dep()
447 if (reg->flags & IR3_REG_HALF) in add_reg_dep()
460 foreach_src_n (reg, i, node->instr) { in calculate_deps()
461 if (reg->flags & (IR3_REG_CONST | IR3_REG_IMMED)) in calculate_deps()
464 if (reg in calculate_deps()
429 add_reg_dep(struct ir3_postsched_deps_state *state, struct ir3_postsched_node *node, const struct ir3_register *reg, unsigned num, int src_n, int dst_n) add_reg_dep() argument
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
H A DMCWin64EH.cpp334 uint8_t b, reg; in ARM64EmitUnwindCode() local
389 assert(inst.Register >= 19 && "Saved reg must be >= 19"); in ARM64EmitUnwindCode()
390 reg = inst.Register - 19; in ARM64EmitUnwindCode()
391 b = 0xD0 | ((reg & 0xC) >> 2); in ARM64EmitUnwindCode()
393 b = ((reg & 0x3) << 6) | (inst.Offset >> 3); in ARM64EmitUnwindCode()
397 assert(inst.Register >= 19 && "Saved reg must be >= 19"); in ARM64EmitUnwindCode()
398 reg = inst.Register - 19; in ARM64EmitUnwindCode()
399 b = 0xD4 | ((reg & 0x8) >> 3); in ARM64EmitUnwindCode()
401 b = ((reg & 0x7) << 5) | ((inst.Offset >> 3) - 1); in ARM64EmitUnwindCode()
406 reg in ARM64EmitUnwindCode()
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/third_party/lzma/Asm/x86/
H A DAesOpt.asm245 XOR_WITH_DATA macro reg, _ppp_
246 pxor reg, [rD + i * 16]
249 WRITE_TO_DATA macro reg, _ppp_
250 movdqa [rD + i * 16], reg
372 AVX__CBC_START macro reg
373 ; vpxor reg, key_ymm, ymmword ptr [rD + 32 * i]
374 vpxor reg, key0_ymm, ymmword ptr [rD + 32 * i]
377 AVX__CBC_END macro reg
379 vpxor reg, reg, iv_ym
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/third_party/node/deps/v8/src/deoptimizer/
H A Dtranslation-array.cc213 void TranslationArrayBuilder::StoreRegister(Register reg) { in StoreRegister() argument
216 Add(reg.code()); in StoreRegister()
219 void TranslationArrayBuilder::StoreInt32Register(Register reg) { in StoreInt32Register() argument
222 Add(reg.code()); in StoreInt32Register()
226 void TranslationArrayBuilder::StoreInt64Register(Register reg) { in StoreInt64Register() argument
229 Add(reg.code()); in StoreInt64Register()
233 void TranslationArrayBuilder::StoreUint32Register(Register reg) { in StoreUint32Register() argument
236 Add(reg.code()); in StoreUint32Register()
239 void TranslationArrayBuilder::StoreBoolRegister(Register reg) { in StoreBoolRegister() argument
242 Add(reg in StoreBoolRegister()
246 StoreFloatRegister(FloatRegister reg) StoreFloatRegister() argument
252 StoreDoubleRegister(DoubleRegister reg) StoreDoubleRegister() argument
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/third_party/libunwind/libunwind/src/aarch64/
H A DGresume.c159 int reg; in establish_machine_state() local
163 for (reg = 0; reg <= UNW_AARCH64_V31; ++reg) in establish_machine_state()
165 Debug (16, "copying %s %d\n", unw_regname (reg), reg); in establish_machine_state()
166 if (unw_is_fpreg (reg)) in establish_machine_state()
168 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0) in establish_machine_state()
169 as->acc.access_fpreg (as, reg, &fpval, 1, arg); in establish_machine_state()
173 if (tdep_access_reg (c, reg, in establish_machine_state()
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/third_party/node/deps/v8/src/execution/ppc/
H A Dsimulator-ppc.h175 void set_register(int reg, intptr_t value);
176 intptr_t get_register(int reg) const;
177 double get_double_from_register_pair(int reg);
421 T get_simd_register_by_lane(int reg, int lane, in get_simd_register_by_lane() argument
427 CHECK_LT(reg, kNumSIMDRs); in get_simd_register_by_lane()
429 CHECK_GE(reg, 0); in get_simd_register_by_lane()
430 return (reinterpret_cast<T*>(&simd_registers_[reg]))[lane]; in get_simd_register_by_lane()
434 T get_simd_register_bytes(int reg, int byte_from) { in get_simd_register_bytes() argument
437 void* src = bit_cast<uint8_t*>(&simd_registers_[reg]) + from; in get_simd_register_bytes()
444 void set_simd_register_by_lane(int reg, in argument
457 set_simd_register_bytes(int reg, int byte_from, T value) set_simd_register_bytes() argument
464 get_simd_register(int reg) get_simd_register() argument
466 set_simd_register(int reg, const simdr_t& value) set_simd_register() argument
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/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_emit_gv100.h50 emitField(12, 3, insn->getSrc(insn->predSrc)->rep()->reg.data.id); in emitInsn()
139 emitField(pos, 1, insn->getSrc(0)->reg.file == FILE_SHADER_OUTPUT); in emitO()
201 int id = val ? val->reg.data.id : -1; in emitSYS()
210 case SV_TID : id = 0x21 + val->reg.data.sv.index; break; in emitSYS()
211 case SV_CTAID : id = 0x25 + val->reg.data.sv.index; break; in emitSYS()
217 case SV_CLOCK : id = 0x50 + val->reg.data.sv.index; break; in emitSYS()
233 TSSemantic ts = val->reg.data.ts == TS_PQUAD_MACTIVE ? TS_MACTIVE : val->reg.data.ts; in emitBTS()
236 emitField(pos, 5, val->reg.data.id); in emitBTS()
250 val->reg in emitGPR()
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/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_opt_constant_folding.c65 struct qreg reg = inst->src[i]; in constant_fold() local
66 if (reg.file == QFILE_UNIF && in constant_fold()
67 c->uniform_contents[reg.index] == QUNIFORM_CONSTANT) { in constant_fold()
68 ui[i] = c->uniform_data[reg.index]; in constant_fold()
69 } else if (reg.file == QFILE_SMALL_IMM) { in constant_fold()
70 ui[i] = reg.index; in constant_fold()
/third_party/node/deps/v8/src/codegen/loong64/
H A Dconstants-loong64.cc26 const char* Registers::Name(int reg) { in Name() argument
28 if ((0 <= reg) && (reg < kNumSimuRegisters)) { in Name()
29 result = names_[reg]; in Name()
46 while (aliases_[i].reg != kInvalidRegister) { in Number()
48 return aliases_[i].reg; in Number()
/third_party/node/deps/v8/src/codegen/arm/
H A Dconstants-arm.cc54 const char* VFPRegisters::Name(int reg, bool is_double) { in Name() argument
55 DCHECK((0 <= reg) && (reg < kNumVFPRegisters)); in Name()
56 return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)]; in Name()
86 while (aliases_[i].reg != kNoRegister) { in Number()
88 return aliases_[i].reg; in Number()
/third_party/mesa3d/src/imagination/rogue/
H A Drogue_nir_helpers.h44 return alu->dest.dest.reg.reg->index; in nir_alu_dest_regindex()
61 return alu->src[src].src.reg.reg->index; in nir_alu_src_regindex()
91 return intr->dest.reg.reg->index; in nir_intr_dest_regindex()
100 return intr->src[src].reg.reg->index; in nir_intr_src_regindex()
/third_party/node/deps/v8/src/codegen/
H A Dinterface-descriptors.cc24 Register reg = registers[i]; in InitializeRegisters() local
25 DCHECK(reg.is_valid()); in InitializeRegisters()
26 DCHECK(!reglist.has(reg)); in InitializeRegisters()
27 DCHECK_NE(reg, kRootRegister); in InitializeRegisters()
29 DCHECK_NE(reg, kPtrComprCageBaseRegister); in InitializeRegisters()
31 reglist.set(reg); in InitializeRegisters()
120 bool CallInterfaceDescriptor::IsValidFloatParameterRegister(Register reg) { in IsValidFloatParameterRegister() argument
122 return reg.code() % 2 == 0; in IsValidFloatParameterRegister()
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-regalloc.h65 void FreeRegister(Register reg) { free_registers_.set(reg); } in FreeRegister() argument
67 ValueNode* GetRegisterValue(Register reg) const { in GetRegisterValue()
68 DCHECK(!free_registers_.has(reg)); in GetRegisterValue()
69 ValueNode* node = register_values_[reg.code()]; in GetRegisterValue()
84 compiler::AllocatedOperand ForceAllocate(Register reg, ValueNode* node);
85 void SetRegister(Register reg, ValueNode* node);
86 void DropRegisterValue(Register reg);

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