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/third_party/backends/backend/genesys/
H A Dlow.cpp64 case AsicType::GL845: // since only a few reg bits differs we handle both together in create_cmd_set()
1453 dev->initial_regs = dev->reg; in sanei_genesys_asic_init()
/third_party/node/deps/v8/src/codegen/
H A Dinterface-descriptors.h405 bool IsValidFloatParameterRegister(Register reg);
/device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/
H A Dwlioctl.h2795 uint8 txpwr_limit[NUM_PWRCTRL_RATES]; /**< reg and local power limit */
2863 /** number of ppr serialization buffers, it should be reg, board and target */
5812 uint8 reg; /**< regulatory class */ member
7539 uint8 reg; member
7559 uint8 reg; member
11977 uint32 cnt_err_msch_reg; /* error is Dw/disc reg with msch */
13610 uint8 reg; member
13619 uint8 reg; member
13709 uint8 reg; member
/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_main.c496 "failed to query mac statistic reg number, ret = %d\n", in hclge_mac_query_reg_num()
504 "mac statistic reg number is invalid!\n"); in hclge_mac_query_reg_num()
3757 u32 val, reg, reg_bit; in hclge_reset_wait() local
3762 reg = HCLGE_GLOBAL_RESET_REG; in hclge_reset_wait()
3766 reg = HCLGE_GLOBAL_RESET_REG; in hclge_reset_wait()
3770 reg = HCLGE_FUN_RST_ING; in hclge_reset_wait()
3780 val = hclge_read_dev(&hdev->hw, reg); in hclge_reset_wait()
3783 val = hclge_read_dev(&hdev->hw, reg); in hclge_reset_wait()
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/component/hdmi/src/mkp/
H A Ddrv_hdmi_intf.c103 hi_void hdmi_set_reg(hi_char *reg) in hdmi_set_reg() argument
105 g_hdmi_reg = reg; in hdmi_set_reg()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c3275 uint32_t reg, uint32_t val) in gfx_v7_0_ring_emit_wreg()
3282 amdgpu_ring_write(ring, reg); in gfx_v7_0_ring_emit_wreg()
4469 /* Privileged reg */ in gfx_v7_0_sw_init()
3274 gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) gfx_v7_0_ring_emit_wreg() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c3782 i915_reg_t reg; member
3792 *batch++ = i915_mmio_reg_offset(lri->reg); in emit_lri()
5293 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The in execlists_init_reg_state()
5554 /* Note: we must use a real engine class for setting up reg state */ in virtual_context_pin()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c3209 uint32_t reg, uint32_t val) in gfx_v7_0_ring_emit_wreg()
3216 amdgpu_ring_write(ring, reg); in gfx_v7_0_ring_emit_wreg()
4410 /* Privileged reg */ in gfx_v7_0_sw_init()
3208 gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) gfx_v7_0_ring_emit_wreg() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c64 #define REG(reg)\
65 hws->regs->reg
/third_party/backends/backend/
H A Dcoolscan.c1132 send_one_LUT (Coolscan_t * s, SANE_Word * LUT, int reg) in send_one_LUT() argument
1154 set_S_datatype_qual_upper (send.cmd, reg); in send_one_LUT()
/third_party/mesa3d/src/imagination/vulkan/
H A Dpvr_cmd_buffer.c782 assert(mrt_resource->u.reg.offset == 0); in pvr_setup_pbe_state()
784 position = mrt_resource->u.reg.out_reg; in pvr_setup_pbe_state()
/third_party/libdrm/tests/amdgpu/
H A Dbasic_tests.c141 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
142 ((reg) & 0xFFFF) | \
3352 /* offset reg in amdgpu_draw_setup_and_write_drawblt_surf_info()
/third_party/node/deps/v8/src/compiler/
H A Dbytecode-graph-builder.cc2218 interpreter::Register reg = bytecode_iterator().GetRegisterOperand(0); in VisitCreateCatchContext() local
2219 Node* exception = environment()->LookupRegister(reg); in VisitCreateCatchContext()
/third_party/skia/third_party/externals/swiftshader/src/OpenGL/compiler/
H A DOutputASM.cpp3198 void OutputASM::declareVarying(TIntermTyped *varying, int reg) in declareVarying() argument
3203 declareVarying(varying->getType(), symbol->getSymbol(), reg); in declareVarying()
/third_party/python/Lib/test/test_email/
H A Dtest_email.py5571 reg = HeaderRegistry()
5572 a = reg('Content-Disposition', 'attachment; 0*00="foo"')
/kernel/linux/linux-5.10/arch/x86/kvm/
H A Dx86.c7054 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) in emulator_read_gpr() argument
7056 return kvm_register_read(emul_to_vcpu(ctxt), reg); in emulator_read_gpr()
7059 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) in emulator_write_gpr() argument
7061 kvm_register_write(emul_to_vcpu(ctxt), reg, val); in emulator_write_gpr() local
/kernel/linux/linux-5.10/drivers/media/usb/gspca/
H A Dzc3xx.c22 #include "zc3xx-reg.h"
5572 u8 reg) in i2c_read()
5579 reg_w(gspca_dev, reg, 0x0092); in i2c_read()
5591 u8 reg, in i2c_write()
5599 reg_w(gspca_dev, reg, 0x92); in i2c_write()
5623 action->val, /* reg */ in usb_exchange()
5629 action->idx >> 8, /* reg */ in usb_exchange()
6303 /* may probe but with no write in reg 0x0010 */ in zcxx_probeSensor()
5571 i2c_read(struct gspca_dev *gspca_dev, u8 reg) i2c_read() argument
5590 i2c_write(struct gspca_dev *gspca_dev, u8 reg, u8 valL, u8 valH) i2c_write() argument
/kernel/linux/linux-6.6/drivers/media/usb/gspca/
H A Dzc3xx.c22 #include "zc3xx-reg.h"
5572 u8 reg) in i2c_read()
5579 reg_w(gspca_dev, reg, 0x0092); in i2c_read()
5591 u8 reg, in i2c_write()
5599 reg_w(gspca_dev, reg, 0x92); in i2c_write()
5623 action->val, /* reg */ in usb_exchange()
5629 action->idx >> 8, /* reg */ in usb_exchange()
6303 /* may probe but with no write in reg 0x0010 */ in zcxx_probeSensor()
5571 i2c_read(struct gspca_dev *gspca_dev, u8 reg) i2c_read() argument
5590 i2c_write(struct gspca_dev *gspca_dev, u8 reg, u8 valL, u8 valH) i2c_write() argument
/kernel/linux/linux-6.6/arch/x86/kvm/
H A Dx86.c8277 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg) in emulator_read_gpr() argument
8279 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg); in emulator_read_gpr()
8282 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val) in emulator_write_gpr() argument
8284 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val); in emulator_write_gpr() local
/kernel/linux/linux-5.10/drivers/net/ethernet/neterion/
H A Ds2io.c2236 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */ in start_nic()
3252 /* Check for the expected value of control reg 1 */ in s2io_updt_xpak_counter()
3411 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ in s2io_reset()
4703 * rx_traffic_int reg is an R1 register, writing all 1's in s2io_isr()
4718 * tx_traffic_int reg is an R1 register, writing all 1's in s2io_isr()
5362 u64 reg; in s2io_ethtool_gregs() local
5370 reg = readq(sp->bar0 + i); in s2io_ethtool_gregs()
5371 memcpy((reg_space + i), &reg, 8); in s2io_ethtool_gregs()
/kernel/linux/linux-5.10/drivers/scsi/smartpqi/
H A Dsmartpqi_init.c3781 u32 reg; in pqi_create_admin_queues() local
3795 reg = PQI_ADMIN_IQ_NUM_ELEMENTS | in pqi_create_admin_queues()
3798 writel(reg, &pqi_registers->admin_iq_num_elements); in pqi_create_admin_queues()
/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns3/
H A Dhns3_enet.c5242 u64 reg; in hns3_set_cq_period_mode() local
5246 reg = is_tx ? HNS3_GL1_CQ_MODE_REG : HNS3_GL0_CQ_MODE_REG; in hns3_set_cq_period_mode()
5248 writel(new_mode, handle->kinfo.io_base + reg); in hns3_set_cq_period_mode()
/kernel/linux/linux-6.6/drivers/net/ethernet/neterion/
H A Ds2io.c2238 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */ in start_nic()
3254 /* Check for the expected value of control reg 1 */ in s2io_updt_xpak_counter()
3415 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ in s2io_reset()
4707 * rx_traffic_int reg is an R1 register, writing all 1's in s2io_isr()
4722 * tx_traffic_int reg is an R1 register, writing all 1's in s2io_isr()
5366 u64 reg; in s2io_ethtool_gregs() local
5374 reg = readq(sp->bar0 + i); in s2io_ethtool_gregs()
5375 memcpy((reg_space + i), &reg, 8); in s2io_ethtool_gregs()
/kernel/linux/linux-6.6/kernel/trace/
H A Dtrace_events_hist.c6715 .reg = hist_register_trigger,
6830 .reg = event_enable_register_trigger,
6841 .reg = event_enable_register_trigger,
/third_party/mesa3d/src/intel/vulkan/
H A DgenX_cmd_buffer.c6087 anv_batch_write_reg(&cmd_buffer->batch, GENX(COMMON_SLICE_CHICKEN1), reg) { in cmd_buffer_emit_gfx12_depth_wa()
6088 reg.HIZPlaneOptimizationdisablebit = is_d16_1x_msaa; in cmd_buffer_emit_gfx12_depth_wa()
6089 reg.HIZPlaneOptimizationdisablebitMask = true; in cmd_buffer_emit_gfx12_depth_wa()

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