| /device/soc/rockchip/common/kernel/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_vinstr.c | 328 struct kbase_va_region *reg; in kbasep_vinstr_map_kernel_dump_buffer() local
336 reg = kbase_mem_alloc(kctx, nr_pages, nr_pages, 0, &flags, in kbasep_vinstr_map_kernel_dump_buffer()
338 if (!reg) in kbasep_vinstr_map_kernel_dump_buffer()
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| H A D | mali_kbase_defs.h | 959 void __iomem *reg; member
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| /third_party/lzma/Asm/x86/ |
| H A D | LzmaDecOpt.asm | 582 IsMatchBranch_Pre macro reg
591 IsMatchBranch macro reg
597 CheckLimits macro reg
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| /third_party/skia/third_party/externals/swiftshader/src/Shader/ |
| H A D | VertexRoutine.cpp | 765 UInt reg = *Pointer<UInt>(data + OFFSET(DrawData, vs.reg[i])); in transformFeedback()
771 Pointer<Byte> v = vertex + OFFSET(Vertex, v) + reg * sizeof(float); in transformFeedback()
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| /third_party/wpa_supplicant/wpa_supplicant-2.9/wpa_supplicant/ |
| H A D | ap.c | 1018 struct wps_registrar *reg; in wpa_supplicant_ap_wps_cancel() local
1024 reg = wpa_s->ap_iface->bss[0]->wps->registrar; in wpa_supplicant_ap_wps_cancel()
1025 reg_sel = wps_registrar_wps_cancel(reg); in wpa_supplicant_ap_wps_cancel()
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| /third_party/wpa_supplicant/wpa_supplicant-2.9_standard/wpa_supplicant/ |
| H A D | ap.c | 1267 struct wps_registrar *reg; in wpa_supplicant_ap_wps_cancel() local
1273 reg = wpa_s->ap_iface->bss[0]->wps->registrar; in wpa_supplicant_ap_wps_cancel()
1274 reg_sel = wps_registrar_wps_cancel(reg); in wpa_supplicant_ap_wps_cancel()
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| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/ |
| H A D | siutils.c | 1520 * for reading 4 bytes from reg 0x200 of d11 core use it like below
1579 * regoff : actual reg offset in si_backplane_access()
2403 /* gpio led powersave reg */ in si_gpioled()
3725 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req) in si_raw_reg() argument
3728 uint32 address_space = reg & ~0xFFF; in si_raw_reg()
3729 volatile uint32 * addr = (void*)(uintptr)(reg); in si_raw_reg()
3752 PCI_SEC_BAR0_WIN_OFFSET + (reg & 0xfff)); in si_raw_reg()
3760 PCI_BAR0_WIN2_OFFSET + (reg & 0xfff)); in si_raw_reg()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 920 T reg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const { in reg() function in v8::internal::Simulator
928 // Common specialized accessors for the reg() template.
930 return reg<int32_t>(code, r31mode); in wreg()
934 return reg<int64_t>(code, r31mode); in xreg()
1017 Instruction* lr() { return reg<Instruction*>(kLinkRegCode); } in lr()
1019 Address get_sp() const { return reg<Address>(31, Reg31IsStackPointer); } in get_sp()
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| /third_party/skia/src/core/ |
| H A D | SkVM.cpp | 1812 static uint8_t mod_rm(Mod mod, int reg, int rm) {
1813 return _233((int)mod, reg, rm);
1839 bool R, // Extra top bit to select ModRM reg, registers 8-15.
1944 this->byte(rex(W1,x>>3,0,dst.reg>>3));
1946 this->byte(mod_rm(Mod::Direct, x, dst.reg&7));
2170 VEX v = vex(w, dst>>3, 0, y.reg>>3,
2174 this->byte(mod_rm(Mod::Direct, dst&7, y.reg&7));
3109 std::vector<Reg> reg(instructions.size());
3131 avail.push_back(reg[input]);
3146 reg[i
[all...] |
| /third_party/mesa3d/src/freedreno/ir3/ |
| H A D | ir3_compiler_nir.c | 119 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
376 dst_sz = alu->dest.dest.reg.reg->num_components; in emit_alu()
962 * assembler won't know what the max address reg is. in emit_intrinsic_load_ubo()
1979 /* Note: the shared reg is initialized to the identity, so we need it to in emit_intrinsic_reduce()
1991 * - Shared reg reduction result, must be initialized to the identity in emit_intrinsic_reduce()
2016 /* shared reg tied source */ in emit_intrinsic_reduce()
2076 * addr reg value can be: in emit_intrinsic()
4401 nir_foreach_register (reg, &fxn->registers) { in emit_instructions()
4402 ir3_declare_array(ctx, reg); in emit_instructions()
4927 struct ir3_register *reg = end->srcs[i]; ir3_compile_shader_nir() local
[all...] |
| /device/soc/rockchip/common/vendor/drivers/gpu/arm/midgard/ |
| H A D | mali_kbase_defs.h | 949 void __iomem *reg;
member
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| /device/soc/rockchip/common/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_wifi6/include/ |
| H A D | event_log_payload.h | 1002 uint8 reg; member
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| /device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/ |
| H A D | mali_kbase_defs.h | 664 * @reg: Kernel virtual address of the region containing GPU
968 void __iomem *reg; member
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-rk3128.c | 91 .reg = RK2928_CLKSEL_CON(1), \
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| /device/soc/rockchip/rk3588/kernel/drivers/pci/ |
| H A D | pci.h | 281 struct resource *res, unsigned int reg);
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| /third_party/libdrm/include/drm/ |
| H A D | radeon_drm.h | 276 unsigned char cmd_type, reg, n_bufs, flags; member
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| /third_party/mesa3d/src/imagination/vulkan/pds/ |
| H A D | pvr_pds.h | 346 * reg - first vertex stream element register to DMA to.
352 uint16_t reg; member
457 /* Structure representing PDS shared reg storing program. */
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| /third_party/mesa3d/src/gallium/drivers/vc4/ |
| H A D | vc4_qir.h | 502 * to the bottom half of physical reg space.
554 struct qreg qir_follow_movs(struct vc4_compile *c, struct qreg reg);
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| /third_party/mesa3d/src/gallium/drivers/svga/include/ |
| H A D | svga3d_cmd.h | 1084 uint32 reg; /* register number */ member
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| /third_party/rust/crates/rustix/src/backend/linux_raw/ |
| H A D | conv.rs | 28 use super::reg::{raw_arg, ArgNumber, ArgReg, RetReg, R0};
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| /third_party/skia/third_party/externals/angle2/src/libANGLE/renderer/d3d/ |
| H A D | ProgramD3D.h | 48 HLSLRegisterType reg,
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| /third_party/mesa3d/src/mesa/x86/ |
| H A D | assyntax.h | 359 #define CODEPTR(reg) CHOICE(*reg, *reg, reg)
1093 #define CODEPTR(reg) P_(reg)
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| H A D | macro-assembler-loong64.cc | 2831 void TurboAssembler::Drop(int count, Condition cond, Register reg, in CallRecordWriteStub() argument
2840 Branch(&skip, NegateCondition(cond), reg, op); in CallRecordWriteStub()
3544 FPURegister reg = FPURegister::from_code(2 * i); in CallRecordWriteStub() local
3545 Fst_d(reg, MemOperand(sp, i * kDoubleSize)); in CallRecordWriteStub()
3580 FPURegister reg = FPURegister::from_code(2 * i); in CallRecordWriteStub() local
3581 Fld_d(reg, MemOperand(t8, i * kDoubleSize)); in CallRecordWriteStub()
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| H A D | bifrost_compile.c | 78 bi_preload(bi_builder *b, unsigned reg) in bi_preload() argument
80 if (bi_is_null(b->shader->preloaded[reg])) { in bi_preload()
86 b->shader->preloaded[reg] = bi_mov_i32(&b_, bi_register(reg)); in bi_preload()
89 return b->shader->preloaded[reg]; in bi_preload()
160 if (vec.reg) { in bi_extract()
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| /third_party/node/deps/v8/src/compiler/backend/riscv64/ |
| H A D | code-generator-riscv64.cc | 638 Register reg = i.InputRegister(0); in AssembleArchInstruction() local
641 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
642 __ CallCodeObject(reg); in AssembleArchInstruction()
673 Register reg = i.InputOrZeroRegister(0); in AssembleArchInstruction() local
676 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
677 __ JumpCodeObject(reg); in AssembleArchInstruction()
698 Register reg = i.InputOrZeroRegister(0); in AssembleArchInstruction() local
701 reg == kJavaScriptCallCodeStartRegister); in AssembleArchInstruction()
702 __ Jump(reg); in AssembleArchInstruction()
|