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/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-bcm2835.c432 * Highest rate for the VCO before we have to use the
487 /* Bitmap encoding which parents accept rate change propagation. */
544 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, in bcm2835_pll_choose_ndiv_and_fdiv() argument
550 div = (u64)rate << A2W_PLL_FRAC_BITS; in bcm2835_pll_choose_ndiv_and_fdiv()
560 u64 rate; in bcm2835_pll_rate_from_divisors() local
565 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); in bcm2835_pll_rate_from_divisors()
566 do_div(rate, pdiv); in bcm2835_pll_rate_from_divisors()
567 return rate >> A2W_PLL_FRAC_BITS; in bcm2835_pll_rate_from_divisors()
570 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, in bcm2835_pll_round_rate() argument
577 rate in bcm2835_pll_round_rate()
678 bcm2835_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) bcm2835_pll_set_rate() argument
808 bcm2835_pll_divider_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) bcm2835_pll_divider_round_rate() argument
855 bcm2835_pll_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) bcm2835_pll_divider_set_rate() argument
934 bcm2835_clock_choose_div(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) bcm2835_clock_choose_div() argument
1072 bcm2835_clock_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) bcm2835_clock_set_rate() argument
1111 bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, int parent_idx, unsigned long rate, u32 *div, unsigned long *prate, unsigned long *avgrate) bcm2835_clock_choose_div_and_prate() argument
1186 unsigned long rate, best_rate = 0; bcm2835_clock_determine_rate() local
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/third_party/pulseaudio/src/pulsecore/
H A Dprotocol-esound.c382 int32_t format, rate; in esd_proto_stream_play() local
397 memcpy(&rate, data, sizeof(int32_t)); in esd_proto_stream_play()
398 rate = PA_MAYBE_INT32_SWAP(c->swap_byte_order, rate); in esd_proto_stream_play()
401 ss.rate = (uint32_t) rate; in esd_proto_stream_play()
471 int32_t format, rate; in esd_proto_stream_record() local
485 memcpy(&rate, data, sizeof(int32_t)); in esd_proto_stream_record()
486 rate = PA_MAYBE_INT32_SWAP(c->swap_byte_order, rate); in esd_proto_stream_record()
585 int32_t rate = 44100, format = ESD_STEREO|ESD_BITS16; esd_proto_server_info() local
634 int32_t id, format = ESD_BITS16 | ESD_STEREO, rate = 44100, lvolume = ESD_VOLUME_BASE, rvolume = ESD_VOLUME_BASE; esd_proto_all_info() local
693 int32_t id, rate, lvolume, rvolume, format, len; esd_proto_all_info() local
835 int32_t format, rate, sc_length; esd_proto_sample_cache() local
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/foundation/graphic/graphic_2d/rosen/test/render_service/render_service_base/unittest/pipeline/
H A Drs_render_frame_rate_linker_test.cpp64 uint32_t rate = 120; in HWTEST_F() local
65 frameRateLinker->SetFrameRate(rate); in HWTEST_F()
66 EXPECT_EQ(frameRateLinker->GetFrameRate(), rate); in HWTEST_F()
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2/
H A Dclock-sh7619.c25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in master_clk_init()
35 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in bus_clk_recalc()
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7203.c29 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; in master_clk_init()
39 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
49 return clk->parent->rate / pfc_divisors[idx-2]; in bus_clk_recalc()
/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dcommon.h45 unsigned long rate);
47 unsigned long rate);
56 const char *name, unsigned long rate);
/kernel/linux/linux-5.10/drivers/clk/sunxi/
H A Dclk-a10-hosc.c23 u32 rate; in sun4i_osc_clk_setup() local
25 if (of_property_read_u32(node, "clock-frequency", &rate)) in sun4i_osc_clk_setup()
28 /* allocate fixed-rate and gate clock structs */ in sun4i_osc_clk_setup()
38 /* set up gate and fixed rate properties */ in sun4i_osc_clk_setup()
42 fixed->fixed_rate = rate; in sun4i_osc_clk_setup()
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7203.c29 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; in master_clk_init()
39 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
49 return clk->parent->rate / pfc_divisors[idx-2]; in bus_clk_recalc()
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2/
H A Dclock-sh7619.c25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in master_clk_init()
35 return clk->parent->rate / pfc_divisors[idx]; in module_clk_recalc()
44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in bus_clk_recalc()
/kernel/linux/linux-5.10/sound/core/
H A Dpcm_iec958.c12 static int create_iec958_consumer(uint rate, uint sample_width, in create_iec958_consumer() argument
20 switch (rate) { in create_iec958_consumer()
84 * @runtime: pcm runtime structure with ->rate filled in
98 return create_iec958_consumer(runtime->rate, in snd_pcm_create_iec958_consumer()
106 * @params: the hw_params instance for extracting rate and sample format
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dcommon.h45 unsigned long rate);
47 unsigned long rate);
56 const char *name, unsigned long rate);
/kernel/linux/linux-6.6/drivers/clk/sunxi/
H A Dclk-a10-hosc.c23 u32 rate; in sun4i_osc_clk_setup() local
25 if (of_property_read_u32(node, "clock-frequency", &rate)) in sun4i_osc_clk_setup()
28 /* allocate fixed-rate and gate clock structs */ in sun4i_osc_clk_setup()
38 /* set up gate and fixed rate properties */ in sun4i_osc_clk_setup()
42 fixed->fixed_rate = rate; in sun4i_osc_clk_setup()
/kernel/linux/linux-6.6/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dhtb.h26 u32 parent_classid, u64 rate, u64 ceil,
30 u64 rate, u64 ceil, struct netlink_ext_ack *extack);
37 mlx5e_htb_node_modify(struct mlx5e_htb *htb, u16 classid, u64 rate, u64 ceil,
/kernel/linux/linux-5.10/sound/soc/meson/
H A Daxg-spdifin.c61 * It would have been nice to check the actual rate against the sample rate
78 unsigned int stat, mode, rate = 0; in axg_spdifin_get_rate() local
90 rate = priv->conf->mode_rates[mode]; in axg_spdifin_get_rate()
92 return rate; in axg_spdifin_get_rate()
149 unsigned int rate) in axg_spdifin_mode_timer()
155 return rate / (128 * priv->conf->mode_rates[mode]); in axg_spdifin_mode_timer()
161 unsigned int rate, t_next; in axg_spdifin_sample_mode_config() local
167 dev_err(dai->dev, "reference clock rate set failed\n"); in axg_spdifin_sample_mode_config()
172 * The rate actuall in axg_spdifin_sample_mode_config()
147 axg_spdifin_mode_timer(struct axg_spdifin *priv, int mode, unsigned int rate) axg_spdifin_mode_timer() argument
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/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-cs2000-cp.c308 static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate, in cs2000_round_rate() argument
314 ratio = cs2000_rate_to_ratio(*parent_rate, rate, priv->lf_ratio); in cs2000_round_rate()
320 unsigned long rate, in cs2000_select_ratio_mode()
334 priv->lf_ratio = priv->dynamic_mode && ((rate / parent_rate) > 4096); in cs2000_select_ratio_mode()
341 unsigned long rate, unsigned long parent_rate) in __cs2000_set_rate()
350 ret = cs2000_select_ratio_mode(priv, rate, parent_rate); in __cs2000_set_rate()
354 ret = cs2000_ratio_set(priv, ch, parent_rate, rate); in __cs2000_set_rate()
366 priv->saved_rate = rate; in __cs2000_set_rate()
373 unsigned long rate, unsigned long parent_rate) in cs2000_set_rate()
378 return __cs2000_set_rate(priv, ch, rate, parent_rat in cs2000_set_rate()
319 cs2000_select_ratio_mode(struct cs2000_priv *priv, unsigned long rate, unsigned long parent_rate) cs2000_select_ratio_mode() argument
340 __cs2000_set_rate(struct cs2000_priv *priv, int ch, unsigned long rate, unsigned long parent_rate) __cs2000_set_rate() argument
372 cs2000_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) cs2000_set_rate() argument
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/kernel/linux/linux-6.6/sound/soc/intel/boards/
H A Dbytcr_wm5102.c52 static int byt_wm5102_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, int rate) in byt_wm5102_prepare_and_enable_pll1() argument
55 int sr_mult = ((rate % 4000) == 0) ? in byt_wm5102_prepare_and_enable_pll1()
56 (WM5102_MAX_SYSCLK_4K / rate) : in byt_wm5102_prepare_and_enable_pll1()
57 (WM5102_MAX_SYSCLK_11025 / rate); in byt_wm5102_prepare_and_enable_pll1()
66 MCLK_FREQ, rate * sr_mult); in byt_wm5102_prepare_and_enable_pll1()
73 ARIZONA_CLK_SRC_FLL1, rate * sr_mult, in byt_wm5102_prepare_and_enable_pll1()
81 rate * 512, SND_SOC_CLOCK_IN); in byt_wm5102_prepare_and_enable_pll1()
219 * To change the rate we must disable the clock first to cover these in byt_wm5102_init()
230 dev_err(card->dev, "Error setting MCLK rate: %d\n", ret); in byt_wm5102_init()
252 struct snd_interval *rate in byt_wm5102_codec_fixup() local
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/kernel/linux/linux-6.6/sound/soc/meson/
H A Daxg-spdifin.c61 * It would have been nice to check the actual rate against the sample rate
78 unsigned int stat, mode, rate = 0; in axg_spdifin_get_rate() local
90 rate = priv->conf->mode_rates[mode]; in axg_spdifin_get_rate()
92 return rate; in axg_spdifin_get_rate()
149 unsigned int rate) in axg_spdifin_mode_timer()
155 return rate / (128 * priv->conf->mode_rates[mode]); in axg_spdifin_mode_timer()
161 unsigned int rate, t_next; in axg_spdifin_sample_mode_config() local
167 dev_err(dai->dev, "reference clock rate set failed\n"); in axg_spdifin_sample_mode_config()
172 * The rate actuall in axg_spdifin_sample_mode_config()
147 axg_spdifin_mode_timer(struct axg_spdifin *priv, int mode, unsigned int rate) axg_spdifin_mode_timer() argument
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/device/soc/rockchip/common/sdk_linux/include/soc/rockchip/
H A Dscpi.h30 int scpi_clk_set_val(u16 clk_id, unsigned long rate);
42 int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
55 static inline int scpi_clk_set_val(u16 clk_id, unsigned long rate) in scpi_clk_set_val() argument
110 static inline int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type) in scpi_ddr_set_clk_rate() argument
/device/soc/rockchip/rk3588/kernel/include/soc/rockchip/
H A Dscpi.h30 int scpi_clk_set_val(u16 clk_id, unsigned long rate);
43 int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type);
56 static inline int scpi_clk_set_val(u16 clk_id, unsigned long rate) in scpi_clk_set_val() argument
112 static inline int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type) in scpi_ddr_set_clk_rate() argument
/kernel/linux/linux-5.10/arch/arm/kernel/
H A Dtopology.c98 const __be32 *rate; in parse_dt_topology() local
122 rate = of_get_property(cn, "clock-frequency", &len); in parse_dt_topology()
123 if (!rate || len != 4) { in parse_dt_topology()
128 capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency; in parse_dt_topology()
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-periph-fixed.c55 unsigned long long rate; in tegra_clk_periph_fixed_recalc_rate() local
57 rate = (unsigned long long)parent_rate * fixed->mul; in tegra_clk_periph_fixed_recalc_rate()
58 do_div(rate, fixed->div); in tegra_clk_periph_fixed_recalc_rate()
60 return (unsigned long)rate; in tegra_clk_periph_fixed_recalc_rate()
/kernel/linux/linux-5.10/drivers/clk/mxs/
H A Dclk-div.c43 static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate, in clk_div_round_rate() argument
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
51 static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate, in clk_div_set_rate() argument
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dclksrc_st_lpc.c45 unsigned long rate; in st_clksrc_init() local
50 rate = clk_get_rate(ddata.clk); in st_clksrc_init()
52 sched_clock_register(st_clksrc_sched_clock_read, 32, rate); in st_clksrc_init()
55 "clksrc-st-lpc", rate, 300, 32, in st_clksrc_init()
81 pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n"); in st_clksrc_setup_clk()
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-fixup-div.c44 static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate, in clk_fixup_div_round_rate() argument
49 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate); in clk_fixup_div_round_rate()
52 static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate, in clk_fixup_div_set_rate() argument
61 divider = parent_rate / rate; in clk_fixup_div_set_rate()
/kernel/linux/linux-5.10/drivers/clk/berlin/
H A Dberlin2-pll.c47 u64 rate = parent_rate; in berlin2_pll_recalc_rate() local
66 rate *= fbdiv * map->mult; in berlin2_pll_recalc_rate()
67 do_div(rate, rfdiv * vcodiv); in berlin2_pll_recalc_rate()
69 return (unsigned long)rate; in berlin2_pll_recalc_rate()

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