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Searched refs:dclk (Results 76 - 100 of 161) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/solomon/
H A Dssd130x.c328 u32 precharge, dclk, com_invdir, compins, chargepump, seg_remap; in ssd130x_init() local
362 dclk = (SSD130X_SET_CLOCK_DIV_SET(ssd130x->dclk_div - 1) | in ssd130x_init()
364 ret = ssd130x_write_cmd(ssd130x, 2, SSD130X_SET_CLOCK_FREQ, dclk); in ssd130x_init()
982 if (device_property_read_u32(dev, "solomon,dclk-div", &ssd130x->dclk_div)) in ssd130x_parse_properties()
984 if (device_property_read_u32(dev, "solomon,dclk-frq", &ssd130x->dclk_frq)) in ssd130x_parse_properties()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dni_dpm.c3518 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3525 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3536 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3543 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3907 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ni_parse_pplib_non_clock_info()
3910 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in ni_parse_pplib_non_clock_info()
3913 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
4293 printk("\tuvd vclk: %d dclk in ni_dpm_print_power_state()
[all...]
H A Dkv_dpm.c837 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
843 (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk); in kv_populate_uvd_table()
852 table->entries[i].dclk, false, &dividers); in kv_populate_uvd_table()
2222 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2596 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in kv_parse_pplib_non_clock_info()
2599 rps->dclk = 0; in kv_parse_pplib_non_clock_info()
2856 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in kv_dpm_print_power_state()
H A Drv770.c49 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
51 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
58 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
60 /* bypass vclk and dclk with bclk */ in rv770_set_uvd_clocks()
65 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
71 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
H A Dradeon.h1344 u32 dclk; member
1430 u32 dclk; member
1701 unsigned vclk, unsigned dclk,
1966 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
H A Dsi_dpm.c2263 radeon_state->vclk && radeon_state->dclk) in si_should_disable_uvd_powertune()
3004 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
5151 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) in si_is_state_ulv_compatible()
5188 if (radeon_state->vclk && radeon_state->dclk) { in si_convert_power_state_to_smc()
6699 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in si_parse_pplib_non_clock_info()
6702 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in si_parse_pplib_non_clock_info()
6705 rps->dclk = 0; in si_parse_pplib_non_clock_info()
7089 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); in si_dpm_debugfs_print_current_performance_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dni_dpm.c3519 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3537 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3544 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3908 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); in ni_parse_pplib_non_clock_info()
3911 rps->dclk = RV770_DEFAULT_DCLK_FREQ; in ni_parse_pplib_non_clock_info()
3914 rps->dclk = 0; in ni_parse_pplib_non_clock_info()
4294 printk("\tuvd vclk: %d dclk in ni_dpm_print_power_state()
[all...]
H A Drv770.c52 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
54 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in rv770_set_uvd_clocks() argument
61 return evergreen_set_uvd_clocks(rdev, vclk, dclk); in rv770_set_uvd_clocks()
63 /* bypass vclk and dclk with bclk */ in rv770_set_uvd_clocks()
68 if (!vclk || !dclk) { in rv770_set_uvd_clocks()
74 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, in rv770_set_uvd_clocks()
H A Dradeon.h1337 u32 dclk; member
1423 u32 dclk; member
1694 unsigned vclk, unsigned dclk,
1955 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
H A Dhwmgr.h110 uint32_t dclk; member
137 uint32_t dclk; member
H A Damdgpu_smu.h133 uint32_t dclk; member
218 uint32_t dclk; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhwmgr.h110 uint32_t dclk; member
137 uint32_t dclk; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h182 uint32_t dclk; member
289 uint32_t dclk; member
/kernel/linux/linux-5.10/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c973 int width, dclk, i, j; /*, refresh; */ in savagefb_decode_var() local
1016 dclk = timings.Clock; in savagefb_decode_var()
1021 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) in savagefb_decode_var()
1028 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1035 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1080 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r); in savagefb_decode_var()
1413 /* restore extended seq regs for dclk */ in savagefb_set_par_int()
1427 /* load new m, n pll values for dclk & mclk */ in savagefb_set_par_int()
/kernel/linux/linux-6.6/drivers/video/fbdev/savage/
H A Dsavagefb_driver.c977 int width, dclk, i, j; /*, refresh; */ in savagefb_decode_var() local
1020 dclk = timings.Clock; in savagefb_decode_var()
1025 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)) in savagefb_decode_var()
1032 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1039 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))) in savagefb_decode_var()
1084 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r); in savagefb_decode_var()
1417 /* restore extended seq regs for dclk */ in savagefb_set_par_int()
1431 /* load new m, n pll values for dclk & mclk */ in savagefb_set_par_int()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/
H A Dsi_dpm.c2352 amdgpu_state->vclk && amdgpu_state->dclk) in si_should_disable_uvd_powertune()
3160 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3167 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3178 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3185 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3459 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
5610 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) in si_is_state_ulv_compatible()
5647 if (amdgpu_state->vclk && amdgpu_state->dclk) { in si_convert_power_state_to_smc()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c2367 amdgpu_state->vclk && amdgpu_state->dclk) in si_should_disable_uvd_powertune()
3175 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_before_set_eng_clock()
3182 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_before_set_eng_clock()
3193 (new_ps->dclk == old_ps->dclk)) in ni_set_uvd_clock_after_set_eng_clock()
3200 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); in ni_set_uvd_clock_after_set_eng_clock()
3474 if (rps->vclk || rps->dclk) { in si_apply_state_adjust_rules()
5652 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) in si_is_state_ulv_compatible()
5689 if (amdgpu_state->vclk && amdgpu_state->dclk) { in si_convert_power_state_to_smc()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.h114 uint32_t dclk; member
H A Dvega10_hwmgr.c1407 dep_mm_table->entries[i].dclk) { in vega10_setup_default_dpm_tables()
1409 dep_mm_table->entries[i].dclk; in vega10_setup_default_dpm_tables()
2122 dep_table->entries[i].dclk == in vega10_populate_smc_uvd_levels()
3219 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; in vega10_get_pp_table_entry()
4843 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); in vega10_check_states_equal()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_hwmgr.h114 uint32_t dclk; member
/kernel/linux/linux-5.10/drivers/mfd/
H A Dsi476x-cmd.c487 * @dclk: DCLK pin function configuration:
521 enum si476x_dclk_config dclk, in si476x_core_cmd_dig_audio_pin_cfg()
528 PIN_CFG_BYTE(dclk), in si476x_core_cmd_dig_audio_pin_cfg()
520 si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *core, enum si476x_dclk_config dclk, enum si476x_dfs_config dfs, enum si476x_dout_config dout, enum si476x_xout_config xout) si476x_core_cmd_dig_audio_pin_cfg() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.c94 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
/kernel/linux/linux-6.6/drivers/mfd/
H A Dsi476x-cmd.c487 * @dclk: DCLK pin function configuration:
521 enum si476x_dclk_config dclk, in si476x_core_cmd_dig_audio_pin_cfg()
528 PIN_CFG_BYTE(dclk), in si476x_core_cmd_dig_audio_pin_cfg()
520 si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *core, enum si476x_dclk_config dclk, enum si476x_dfs_config dfs, enum si476x_dout_config dout, enum si476x_xout_config xout) si476x_core_cmd_dig_audio_pin_cfg() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dvi.c1027 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in vi_set_uvd_clocks() argument
1036 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS); in vi_set_uvd_clocks()
1044 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); in vi_set_uvd_clocks()
H A Dsoc21.c418 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc21_set_uvd_clocks() argument

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