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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/
H A Di915_gem_clflush.c15 struct dma_fence_work base; member
27 static int clflush_work(struct dma_fence_work *base) in clflush_work() argument
29 struct clflush *clflush = container_of(base, typeof(*clflush), base); in clflush_work()
43 static void clflush_release(struct dma_fence_work *base) in clflush_release() argument
45 struct clflush *clflush = container_of(base, typeof(*clflush), base); in clflush_release()
66 dma_fence_work_init(&clflush->base, &clflush_ops); in clflush_work_create()
109 i915_sw_fence_await_reservation(&clflush->base.chain, in i915_gem_clflush_object()
110 obj->base in i915_gem_clflush_object()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.h38 #define RING_ELSP(base) _MMIO((base) + 0x230)
39 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
40 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
41 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
47 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base)
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/kernel/linux/linux-5.10/drivers/remoteproc/
H A Dqcom_pil_info.c16 * region followed by a 64 bit base address and 32 bit size, both little
23 void __iomem *base; member
34 void __iomem *base; in qcom_pil_info_init() local
38 if (_reloc.base) in qcom_pil_info_init()
50 base = ioremap(imem.start, resource_size(&imem)); in qcom_pil_info_init()
51 if (!base) { in qcom_pil_info_init()
56 memset_io(base, 0, resource_size(&imem)); in qcom_pil_info_init()
58 _reloc.base = base; in qcom_pil_info_init()
67 * @base
72 qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) qcom_pil_info_store() argument
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/kernel/linux/linux-6.6/drivers/remoteproc/
H A Dqcom_pil_info.c16 * region followed by a 64 bit base address and 32 bit size, both little
23 void __iomem *base; member
34 void __iomem *base; in qcom_pil_info_init() local
38 if (_reloc.base) in qcom_pil_info_init()
50 base = ioremap(imem.start, resource_size(&imem)); in qcom_pil_info_init()
51 if (!base) { in qcom_pil_info_init()
56 memset_io(base, 0, resource_size(&imem)); in qcom_pil_info_init()
58 _reloc.base = base; in qcom_pil_info_init()
67 * @base
72 qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) qcom_pil_info_store() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dccg.c31 container_of(dccg, struct dcn_dccg, base)
41 dccg_dcn->base.ctx
62 struct dccg *base; in dccg3_create() local
69 base = &dccg_dcn->base; in dccg3_create()
70 base->ctx = ctx; in dccg3_create()
71 base->funcs = &dccg3_funcs; in dccg3_create()
77 return &dccg_dcn->base; in dccg3_create()
87 struct dccg *base; in dccg30_create() local
94 base in dccg30_create()
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/third_party/gn/src/gn/
H A Dcommand_clean.cc5 #include "base/files/file_enumerator.h"
6 #include "base/files/file_path.h"
7 #include "base/files/file_util.h"
8 #include "base/strings/string_util.h"
9 #include "base/strings/stringprintf.h"
24 base::FilePath build_dir(setup->build_settings().GetFullPath( in CleanOneDir()
29 base::FilePath args_gn_file = build_dir.AppendASCII("args.gn"); in CleanOneDir()
30 base::FilePath build_ninja_d_file = build_dir.AppendASCII("build.ninja.d"); in CleanOneDir()
31 if (!base::PathExists(args_gn_file) && in CleanOneDir()
32 !base in CleanOneDir()
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/third_party/FreeBSD/lib/libc/stdlib/
H A Dstrtoimax.c56 strtoimax_l(const char * __restrict nptr, char ** __restrict endptr, int base) in strtoimax_l() argument
67 * If base is 0, allow 0x for hex and 0 for octal, else in strtoimax_l()
68 * assume decimal; if base is already 16, allow 0x. in strtoimax_l()
83 if ((base == 0 || base == 16) && in strtoimax_l()
90 base = 16; in strtoimax_l()
92 if (base == 0) { in strtoimax_l()
93 base = c == '0' ? 8 : 10; in strtoimax_l()
96 if (base < 2 || base > 3 in strtoimax_l()
158 strtoimax(const char * __restrict nptr, char ** __restrict endptr, int base) strtoimax() argument
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H A Dstrtoumax.c56 strtoumax_l(const char * __restrict nptr, char ** __restrict endptr, int base) in strtoumax_l() argument
81 if ((base == 0 || base == 16) && in strtoumax_l()
88 base = 16; in strtoumax_l()
90 if (base == 0) { in strtoumax_l()
91 base = c == '0' ? 8 : 10; in strtoumax_l()
94 if (base < 2 || base > 36) { in strtoumax_l()
98 cutoff = UINTMAX_MAX / base; in strtoumax_l()
99 cutlim = UINTMAX_MAX % base; in strtoumax_l()
136 strtoumax(const char * __restrict nptr, char ** __restrict endptr, int base) strtoumax() argument
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H A Dstrtoul.c56 strtoul_l(const char * __restrict nptr, char ** __restrict endptr, int base) in strtoul_l() argument
81 if ((base == 0 || base == 16) && in strtoul_l()
88 base = 16; in strtoul_l()
90 if (base == 0) { in strtoul_l()
91 base = c == '0' ? 8 : 10; in strtoul_l()
94 if (base < 2 || base > 36) { in strtoul_l()
98 cutoff = ULONG_MAX / base; in strtoul_l()
99 cutlim = ULONG_MAX % base; in strtoul_l()
136 strtoul(const char * __restrict nptr, char ** __restrict endptr, int base) strtoul() argument
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/third_party/mesa3d/src/amd/vulkan/winsys/null/
H A Dradv_null_cs.c32 struct radeon_cmdbuf base; member
37 radv_null_cs(struct radeon_cmdbuf *base) in radv_null_cs() argument
39 return (struct radv_null_cs *)base; in radv_null_cs()
77 cs->base.buf = malloc(16384); in radv_null_cs_create()
78 cs->base.max_dw = 4096; in radv_null_cs_create()
79 if (!cs->base.buf) { in radv_null_cs_create()
84 return &cs->base; in radv_null_cs_create()
97 FREE(cs->base.buf); in radv_null_cs_destroy()
104 ws->base.ctx_create = radv_null_ctx_create; in radv_null_cs_init_functions()
105 ws->base in radv_null_cs_init_functions()
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/third_party/node/deps/v8/third_party/zlib/google/
H A Dzip_writer.h11 #include "base/files/file_path.h"
12 #include "base/time/time.h"
44 static std::unique_ptr<ZipWriter> Create(const base::FilePath& zip_file,
55 void SetProgressCallback(ProgressCallback callback, base::TimeDelta period) { in SetProgressCallback()
76 bool AddDirectoryContents(const base::FilePath& path);
95 bool AddFileContent(const base::FilePath& path, base::File file);
98 bool AddFileEntry(const base::FilePath& path, base::File file);
105 bool AddDirectoryEntry(const base
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/third_party/node/deps/zlib/google/
H A Dzip_writer.h11 #include "base/files/file_path.h"
12 #include "base/time/time.h"
44 static std::unique_ptr<ZipWriter> Create(const base::FilePath& zip_file,
55 void SetProgressCallback(ProgressCallback callback, base::TimeDelta period) { in SetProgressCallback()
76 bool AddDirectoryContents(const base::FilePath& path);
95 bool AddFileContent(const base::FilePath& path, base::File file);
98 bool AddFileEntry(const base::FilePath& path, base::File file);
105 bool AddDirectoryEntry(const base
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/third_party/musl/porting/linux/user/src/stdlib/
H A Dstrtol.c8 static unsigned long long strtox(const char *s, char **p, int base, unsigned long long lim) in strtox() argument
13 unsigned long long y = __intscan(&f, base, 1, lim); in strtox()
21 unsigned long long strtoull(const char *restrict s, char **restrict p, int base) in strtoull() argument
23 return strtox(s, p, base, ULLONG_MAX); in strtoull()
26 long long strtoll(const char *restrict s, char **restrict p, int base) in strtoll() argument
28 return strtox(s, p, base, LLONG_MIN); in strtoll()
31 unsigned long strtoul_weak(const char *restrict s, char **restrict p, int base) in strtoul_weak() argument
33 return strtox(s, p, base, ULONG_MAX); in strtoul_weak()
36 long strtol(const char *restrict s, char **restrict p, int base) in strtol() argument
38 return strtox(s, p, base, in strtol()
41 strtoimax_weak(const char *restrict s, char **restrict p, int base) strtoimax_weak() argument
46 strtoumax_weak(const char *restrict s, char **restrict p, int base) strtoumax_weak() argument
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/third_party/mesa3d/src/gallium/auxiliary/driver_trace/
H A Dtr_texture.c53 memcpy(&tr_surf->base, surface, sizeof(struct pipe_surface)); in trace_surf_create()
54 tr_surf->base.context = &tr_ctx->base; in trace_surf_create()
56 pipe_reference_init(&tr_surf->base.reference, 1); in trace_surf_create()
57 tr_surf->base.texture = NULL; in trace_surf_create()
58 pipe_resource_reference(&tr_surf->base.texture, res); in trace_surf_create()
61 return &tr_surf->base; in trace_surf_create()
72 pipe_resource_reference(&tr_surf->base.texture, NULL); in trace_surf_destroy()
92 memcpy(&tr_trans->base, transfer, tr_ctx->threaded ? sizeof(struct threaded_transfer) : sizeof(struct pipe_transfer)); in trace_transfer_create()
94 tr_trans->base in trace_transfer_create()
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/third_party/skia/src/sksl/ir/
H A DSkSLFieldAccess.cpp19 std::unique_ptr<Expression> base, in Convert()
21 const Type& baseType = base->type(); in Convert()
32 context, base->fLine, std::move(base), f); in Convert()
37 context, base->fLine, std::move(base), f.functions()); in Convert()
44 base->fLine, in Convert()
52 return FieldAccess::Make(context, std::move(base), (int) i); in Convert()
57 return Setting::Convert(context, base->fLine, field); in Convert()
60 context.fErrors->error(base in Convert()
17 Convert(const Context& context, SymbolTable& symbolTable, std::unique_ptr<Expression> base, skstd::string_view field) Convert() argument
65 Make(const Context& context, std::unique_ptr<Expression> base, int fieldIndex, OwnerKind ownerKind) Make() argument
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/kernel/linux/linux-5.10/drivers/clk/davinci/
H A Dpll-da850.c89 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll0_init() argument
93 davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); in da850_pll0_init()
95 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); in da850_pll0_init()
98 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); in da850_pll0_init()
103 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); in da850_pll0_init()
106 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); in da850_pll0_init()
110 davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); in da850_pll0_init()
112 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); in da850_pll0_init()
115 davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); in da850_pll0_init()
117 davinci_pll_auxclk_register(dev, "pll0_auxclk", base); in da850_pll0_init()
144 void __iomem *base; of_da850_pll0_init() local
198 da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) da850_pll1_init() argument
223 of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) of_da850_pll1_init() argument
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/kernel/linux/linux-6.6/drivers/clk/davinci/
H A Dpll-da850.c89 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll0_init() argument
93 davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); in da850_pll0_init()
95 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); in da850_pll0_init()
98 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); in da850_pll0_init()
103 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); in da850_pll0_init()
106 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); in da850_pll0_init()
110 davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); in da850_pll0_init()
112 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); in da850_pll0_init()
115 davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); in da850_pll0_init()
117 davinci_pll_auxclk_register(dev, "pll0_auxclk", base); in da850_pll0_init()
144 void __iomem *base; of_da850_pll0_init() local
198 da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) da850_pll1_init() argument
223 of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) of_da850_pll1_init() argument
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-ixp4xx.c47 void __iomem *base; member
69 return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); in ixp4xx_read_timer()
89 tmr->base + IXP4XX_OSST_OFFSET); in ixp4xx_timer_interrupt()
102 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_next_event()
106 tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_next_event()
116 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_shutdown()
118 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_shutdown()
128 tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_oneshot()
140 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET); in ixp4xx_set_periodic()
150 val = __raw_readl(tmr->base in ixp4xx_resume()
162 ixp4xx_timer_register(void __iomem *base, int timer_irq, unsigned int timer_freq) ixp4xx_timer_register() argument
266 void __iomem *base; ixp4xx_of_timer_init() local
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-tpdm.c28 val = readl_relaxed(drvdata->base + TPDM_DSB_CR); in tpdm_enable_dsb()
30 writel_relaxed(val, drvdata->base + TPDM_DSB_CR); in tpdm_enable_dsb()
36 CS_UNLOCK(drvdata->base); in __tpdm_enable()
42 CS_LOCK(drvdata->base); in __tpdm_enable()
69 val = readl_relaxed(drvdata->base + TPDM_DSB_CR); in tpdm_disable_dsb()
71 writel_relaxed(val, drvdata->base + TPDM_DSB_CR); in tpdm_disable_dsb()
77 CS_UNLOCK(drvdata->base); in __tpdm_disable()
83 CS_LOCK(drvdata->base); in __tpdm_disable()
117 CS_UNLOCK(drvdata->base); in tpdm_init_default_data()
119 pidr = readl_relaxed(drvdata->base in tpdm_init_default_data()
179 void __iomem *base; tpdm_probe() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.c763 return &aux_engine->base; in dcn32_aux_engine_create()
817 clk_src->base.dp_clk_src = dp_clk_src; in dcn32_clock_source_create()
818 return &clk_src->base; in dcn32_clock_source_create()
878 return &hubbub2->base; in dcn32_hubbub_create()
900 return &hubp2->base; in dcn32_hubp_create()
932 return &dpp3->base; in dcn32_dpp_create()
961 return &mpc30->base; in dcn32_mpc_create()
984 return &opp2->base; in dcn32_opp_create()
1005 tgn10->base.inst = instance; in dcn32_timing_generator_create()
1006 tgn10->base in dcn32_timing_generator_create()
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/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-xgs-iproc.c34 void __iomem *base; member
58 chip->base + IPROC_GPIO_CCA_INT_EVENT); in iproc_gpio_irq_ack()
74 event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); in iproc_gpio_irq_unmask()
75 int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); in iproc_gpio_irq_unmask()
80 chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); in iproc_gpio_irq_unmask()
84 chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); in iproc_gpio_irq_unmask()
100 event_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); in iproc_gpio_irq_mask()
101 int_mask = readl_relaxed(chip->base + IPROC_GPIO_CCA_INT_LEVEL_MASK); in iproc_gpio_irq_mask()
106 chip->base + IPROC_GPIO_CCA_INT_EVENT_MASK); in iproc_gpio_irq_mask()
110 chip->base in iproc_gpio_irq_mask()
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/kernel/linux/linux-5.10/arch/x86/crypto/
H A Dtwofish_avx_glue.c40 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
217 .base.cra_name = "__ecb(twofish)",
218 .base.cra_driver_name = "__ecb-twofish-avx",
219 .base.cra_priority = 400,
220 .base.cra_flags = CRYPTO_ALG_INTERNAL,
221 .base.cra_blocksize = TF_BLOCK_SIZE,
222 .base.cra_ctxsize = sizeof(struct twofish_ctx),
223 .base.cra_module = THIS_MODULE,
230 .base.cra_name = "__cbc(twofish)",
231 .base
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H A Dcast6_avx_glue.c38 return cast6_setkey(&tfm->base, key, keylen); in cast6_setkey_skcipher()
211 .base.cra_name = "__ecb(cast6)",
212 .base.cra_driver_name = "__ecb-cast6-avx",
213 .base.cra_priority = 200,
214 .base.cra_flags = CRYPTO_ALG_INTERNAL,
215 .base.cra_blocksize = CAST6_BLOCK_SIZE,
216 .base.cra_ctxsize = sizeof(struct cast6_ctx),
217 .base.cra_module = THIS_MODULE,
224 .base.cra_name = "__cbc(cast6)",
225 .base
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_link_encoder.c40 enc10->base.ctx
42 enc10->base.ctx->logger
347 enc10->base.funcs = &dcn21_link_enc_funcs; in dcn21_link_encoder_construct()
348 enc10->base.ctx = init_data->ctx; in dcn21_link_encoder_construct()
349 enc10->base.id = init_data->encoder; in dcn21_link_encoder_construct()
351 enc10->base.hpd_source = init_data->hpd_source; in dcn21_link_encoder_construct()
352 enc10->base.connector = init_data->connector; in dcn21_link_encoder_construct()
354 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; in dcn21_link_encoder_construct()
356 enc10->base.features = *enc_features; in dcn21_link_encoder_construct()
358 enc10->base in dcn21_link_encoder_construct()
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/kernel/linux/linux-6.6/arch/powerpc/mm/book3s32/
H A Dmmu.c96 * - base address must be aligned to the block size. So the maximum block size
97 * is identified by the lowest bit set to 1 in the base address (for instance
98 * if base is 0x16000000, max size is 0x02000000).
102 unsigned int bat_block_size(unsigned long base, unsigned long top) in bat_block_size() argument
105 unsigned int base_shift = (ffs(base) - 1) & 31; in bat_block_size()
106 unsigned int block_shift = (fls(top - base) - 1) & 31; in bat_block_size()
142 static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top) in __mmu_mapin_ram() argument
146 while ((idx = find_free_bat()) != -1 && base != top) { in __mmu_mapin_ram()
147 unsigned int size = bat_block_size(base, top); in __mmu_mapin_ram()
151 setbat(idx, PAGE_OFFSET + base, bas in __mmu_mapin_ram()
158 mmu_mapin_ram(unsigned long base, unsigned long top) mmu_mapin_ram() argument
200 unsigned long base = (unsigned long)_stext - PAGE_OFFSET; mmu_mark_initmem_nx() local
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