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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_vma.c42 struct i915_global base; member
123 vma->resv = obj->base.resv; in vma_create()
124 vma->size = obj->base.size; in vma_create()
144 obj->base.size >> PAGE_SHIFT)); in vma_create()
147 GEM_BUG_ON(vma->size > obj->base.size); in vma_create()
293 struct dma_fence_work base; member
305 struct i915_vma_work *vw = container_of(work, typeof(*vw), base); in __vma_bind()
315 struct i915_vma_work *vw = container_of(work, typeof(*vw), base); in __vma_release()
340 dma_fence_work_init(&vw->base, &bind_ops); in i915_vma_work()
341 vw->base in i915_vma_work()
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/kernel/linux/linux-5.10/drivers/gpu/drm/qxl/
H A Dqxl_display.c156 drm_object_property_set_value(&connector->base, in qxl_update_offset_props()
158 drm_object_property_set_value(&connector->base, in qxl_update_offset_props()
790 (&qdev->dumb_shadow_bo->tbo.base); in qxl_plane_prepare_fb()
800 (&user_bo->shadow->tbo.base); in qxl_plane_prepare_fb()
803 drm_gem_object_get(&qdev->dumb_shadow_bo->tbo.base); in qxl_plane_prepare_fb()
834 drm_gem_object_put(&user_bo->shadow->tbo.base); in qxl_plane_cleanup_fb()
948 r = drm_crtc_init_with_planes(dev, &qxl_crtc->base, primary, cursor, in qdev_crtc_init()
954 drm_crtc_helper_add(&qxl_crtc->base, &qxl_crtc_helper_funcs); in qdev_crtc_init()
1089 connector = &qxl_output->base; in qdev_output_init()
1091 drm_connector_init(dev, &qxl_output->base, in qdev_output_init()
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/kernel/linux/linux-5.10/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.c253 static const u16 base[] = { 0x40, 0x60, 0x80 }; in b43_phy_ht_zero_extg() local
255 for (i = 0; i < ARRAY_SIZE(base); i++) { in b43_phy_ht_zero_extg()
257 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0); in b43_phy_ht_zero_extg()
260 for (i = 0; i < ARRAY_SIZE(base); i++) in b43_phy_ht_zero_extg()
261 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0); in b43_phy_ht_zero_extg()
576 static const u16 base[] = { 0x840, 0x860, 0x880 }; in b43_phy_ht_tx_power_ctl_idle_tssi() local
582 save_regs[core][1] = b43_phy_read(dev, base[core] + 6); in b43_phy_ht_tx_power_ctl_idle_tssi()
583 save_regs[core][2] = b43_phy_read(dev, base[core] + 7); in b43_phy_ht_tx_power_ctl_idle_tssi()
584 save_regs[core][0] = b43_phy_read(dev, base[core] + 0); in b43_phy_ht_tx_power_ctl_idle_tssi()
586 b43_phy_write(dev, base[cor in b43_phy_ht_tx_power_ctl_idle_tssi()
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/kernel/linux/linux-5.10/drivers/net/vmxnet3/
H A Dvmxnet3_ethtool.c400 u8 *base; in vmxnet3_get_ethtool_stats() local
410 base = (u8 *)&adapter->tqd_start[j].stats; in vmxnet3_get_ethtool_stats()
413 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
416 base = (u8 *)&adapter->tx_queue[j].stats; in vmxnet3_get_ethtool_stats()
418 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
423 base = (u8 *)&adapter->rqd_start[j].stats; in vmxnet3_get_ethtool_stats()
426 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
429 base = (u8 *)&adapter->rx_queue[j].stats; in vmxnet3_get_ethtool_stats()
431 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
435 base in vmxnet3_get_ethtool_stats()
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/kernel/linux/linux-5.10/sound/soc/codecs/
H A Dcs47l24.c41 { .type = WMFW_ADSP2_PM, .base = 0x200000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x280000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x290000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x2a8000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x300000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x380000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x390000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x3a8000 },
85 #define CS47L24_NG_SRC(name, base) \
86 SOC_SINGLE(name " NG HPOUT1L Switch", base,
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_fbc.c646 * programmed as the display plane base address register. It does not look at
652 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_hw_tracking_covers_screen()
698 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_update_state_cache()
798 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_can_activate()
916 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_get_reg_params()
931 params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane; in intel_fbc_get_reg_params()
947 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_can_flip_nuke()
982 struct intel_plane *plane = to_intel_plane(crtc->base.primary); in intel_fbc_pre_update()
987 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_fbc_pre_update()
1056 struct drm_i915_private *dev_priv = to_i915(crtc->base in __intel_fbc_post_update()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
H A Dnouveau_connector.c298 drm_object_attach_property(&connector->base, dev->mode_config. in nouveau_conn_attach_properties()
307 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
310 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
312 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
318 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
322 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
335 drm_object_attach_property(&connector->base, dev->mode_config. in nouveau_conn_attach_properties()
348 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
353 drm_object_attach_property(&connector->base, in nouveau_conn_attach_properties()
524 drm_object_property_set_value(&connector->base, in nouveau_connector_set_encoder()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/xlnx/
H A Dzynqmp_disp.c164 * @base: Registers I/O base address
167 void __iomem *base; member
172 * @base: Registers I/O base address
175 void __iomem *base; member
180 * @base: Registers I/O base address
185 void __iomem *base; member
429 return readl(avbuf->base in zynqmp_disp_avbuf_read()
[all...]
/kernel/linux/linux-5.10/drivers/pcmcia/
H A Dyenta_socket.c86 u32 val = readl(socket->base + reg); in cb_readl()
94 writel(val, socket->base + reg); in cb_writel()
95 readl(socket->base + reg); /* avoid problems with PCI write posting */ in cb_writel()
142 u8 val = readb(socket->base + 0x800 + reg); in exca_readb()
150 val = readb(socket->base + 0x800 + reg); in exca_readw()
151 val |= readb(socket->base + 0x800 + reg + 1) << 8; in exca_readw()
159 writeb(val, socket->base + 0x800 + reg); in exca_writeb()
160 readb(socket->base + 0x800 + reg); /* PCI write posting... */ in exca_writeb()
166 writeb(val, socket->base + 0x800 + reg); in exca_writew()
167 writeb(val >> 8, socket->base in exca_writew()
[all...]
/kernel/linux/linux-6.6/drivers/fsi/
H A Dfsi-master-ast-cf.c77 * System register base address (needed for configuring the
759 void __iomem *base) in setup_common_fw_config()
761 iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR); in setup_common_fw_config()
762 iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR); in setup_common_fw_config()
763 iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR); in setup_common_fw_config()
764 iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR); in setup_common_fw_config()
765 iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR); in setup_common_fw_config()
766 iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR); in setup_common_fw_config()
767 iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT); in setup_common_fw_config()
768 iowrite8(master->gpio_dat_bit, base in setup_common_fw_config()
758 setup_common_fw_config(struct fsi_master_acf *master, void __iomem *base) setup_common_fw_config() argument
774 void __iomem *base = master->cf_mem + HDR_OFFSET; setup_ast2500_fw_config() local
782 void __iomem *base = master->cf_mem + HDR_OFFSET; setup_ast2400_fw_config() local
[all...]
/kernel/linux/linux-6.6/drivers/dma/
H A Dnbpfaxi.c178 * @base: register address base
204 void __iomem *base; member
230 void __iomem *base; member
307 u32 data = ioread32(chan->base + offset); in nbpf_chan_read()
309 __func__, chan->base, offset, data); in nbpf_chan_read()
316 iowrite32(data, chan->base + offset); in nbpf_chan_write()
318 __func__, chan->base, offset, data); in nbpf_chan_write()
324 u32 data = ioread32(nbpf->base + offset); in nbpf_read()
326 __func__, nbpf->base, offse in nbpf_read()
[all...]
/kernel/linux/linux-6.6/drivers/net/vmxnet3/
H A Dvmxnet3_ethtool.c472 u8 *base; in vmxnet3_get_ethtool_stats() local
482 base = (u8 *)&adapter->tqd_start[j].stats; in vmxnet3_get_ethtool_stats()
485 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
488 base = (u8 *)&adapter->tx_queue[j].stats; in vmxnet3_get_ethtool_stats()
490 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
495 base = (u8 *)&adapter->rqd_start[j].stats; in vmxnet3_get_ethtool_stats()
498 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
501 base = (u8 *)&adapter->rx_queue[j].stats; in vmxnet3_get_ethtool_stats()
503 *buf++ = *(u64 *)(base + in vmxnet3_get_ethtool_stats()
507 base in vmxnet3_get_ethtool_stats()
[all...]
/kernel/linux/linux-6.6/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.c253 static const u16 base[] = { 0x40, 0x60, 0x80 }; in b43_phy_ht_zero_extg() local
255 for (i = 0; i < ARRAY_SIZE(base); i++) { in b43_phy_ht_zero_extg()
257 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0); in b43_phy_ht_zero_extg()
260 for (i = 0; i < ARRAY_SIZE(base); i++) in b43_phy_ht_zero_extg()
261 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0); in b43_phy_ht_zero_extg()
576 static const u16 base[] = { 0x840, 0x860, 0x880 }; in b43_phy_ht_tx_power_ctl_idle_tssi() local
582 save_regs[core][1] = b43_phy_read(dev, base[core] + 6); in b43_phy_ht_tx_power_ctl_idle_tssi()
583 save_regs[core][2] = b43_phy_read(dev, base[core] + 7); in b43_phy_ht_tx_power_ctl_idle_tssi()
584 save_regs[core][0] = b43_phy_read(dev, base[core] + 0); in b43_phy_ht_tx_power_ctl_idle_tssi()
586 b43_phy_write(dev, base[cor in b43_phy_ht_tx_power_ctl_idle_tssi()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_gem.c120 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm; in i915_gem_object_unbind()
282 loff_t base, int offset, in gtt_user_read()
289 vaddr = io_mapping_map_atomic_wc(mapping, base); in gtt_user_read()
295 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); in gtt_user_read()
308 struct drm_i915_private *i915 = to_i915(obj->base.dev); in i915_gem_gtt_prepare()
369 struct drm_i915_private *i915 = to_i915(obj->base.dev); in i915_gem_gtt_cleanup()
385 struct drm_i915_private *i915 = to_i915(obj->base.dev); in i915_gem_gtt_pread()
484 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { in i915_gem_pread_ioctl()
517 loff_t base, int offset, in ggtt_write()
524 vaddr = io_mapping_map_atomic_wc(mapping, base); in ggtt_write()
281 gtt_user_read(struct io_mapping *mapping, loff_t base, int offset, char __user *user_data, int length) gtt_user_read() argument
516 ggtt_write(struct io_mapping *mapping, loff_t base, int offset, char __user *user_data, int length) ggtt_write() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/qxl/
H A Dqxl_display.c160 drm_object_property_set_value(&connector->base, in qxl_update_offset_props()
162 drm_object_property_set_value(&connector->base, in qxl_update_offset_props()
809 (&qdev->dumb_shadow_bo->tbo.base); in qxl_prepare_shadow()
820 (&user_bo->shadow->tbo.base); in qxl_prepare_shadow()
823 drm_gem_object_get(&qdev->dumb_shadow_bo->tbo.base); in qxl_prepare_shadow()
886 drm_gem_object_put(&user_bo->shadow->tbo.base); in qxl_plane_cleanup_fb()
1000 r = drm_crtc_init_with_planes(dev, &qxl_crtc->base, primary, cursor, in qdev_crtc_init()
1006 drm_crtc_helper_add(&qxl_crtc->base, &qxl_crtc_helper_funcs); in qdev_crtc_init()
1141 connector = &qxl_output->base; in qdev_output_init()
1143 drm_connector_init(dev, &qxl_output->base, in qdev_output_init()
[all...]
/kernel/linux/linux-6.6/sound/soc/codecs/
H A Dcs47l24.c41 { .type = WMFW_ADSP2_PM, .base = 0x200000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x280000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x290000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x2a8000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x300000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x380000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x390000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x3a8000 },
85 #define CS47L24_NG_SRC(name, base) \
86 SOC_SINGLE(name " NG HPOUT1L Switch", base,
[all...]
/device/soc/hisilicon/hi3516dv300/sdk_linux/drv/mpp/cbb/
H A DMakefile20 .PHONY:clean all base sys vi mcf vo vo_dev vpss avs chnl region vgs gdc venc vedu vdec vfmw jpegd dis isp audio audio_bin
22 target = base sys
34 HI_COMM_INC_FILE += $(CBB_ROOT)/base/include/hi_comm_vb.h
69 base:
/device/qemu/drivers/char/mmz/
H A Dmmz.c95 vaddr = vmRegion->range.base; in MmzAlloc()
116 mmzm->vaddr = (void *)vmRegion->range.base; in MmzAlloc()
152 mmzm->vaddr = (void *)vmRegion->range.base; in MmzMap()
153 vaddr = vmRegion->range.base; in MmzMap()
/device/soc/rockchip/common/vendor/drivers/video/rockchip/mpp/hack/
H A Dmpp_hack_px30.c154 void __iomem *base; in px30_workaround_combo_init() local
161 base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); in px30_workaround_combo_init()
162 if (IS_ERR(base)) { in px30_workaround_combo_init()
166 iommu->bases[i] = base; in px30_workaround_combo_init()
/device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/
H A Drockchip_drm_fb.c111 rockchip_logo_fb->fb.obj[0] = &rockchip_logo_fb->rk_obj.base; in rockchip_drm_logo_fb_alloc()
201 ret = drm_gem_fb_init_with_funcs(dev, &afbc_fb->base, file, mode_cmd, &rockchip_drm_fb_funcs); in rockchip_fb_create()
212 struct drm_gem_object **obj = afbc_fb->base.obj; in rockchip_fb_create()
223 return &afbc_fb->base; in rockchip_fb_create()
/device/soc/rockchip/rk3588/kernel/drivers/video/rockchip/mpp/hack/
H A Dmpp_hack_px30.c162 void __iomem *base; in px30_workaround_combo_init() local
169 base = devm_ioremap(&pdev->dev, in px30_workaround_combo_init()
171 if (IS_ERR(base)) in px30_workaround_combo_init()
174 iommu->bases[i] = base; in px30_workaround_combo_init()
/kernel/linux/linux-5.10/drivers/firewire/
H A Dnosy.h59 #define DMA_BREG(base, chan) (base + chan * 0x20)
60 #define DMA_SREG(base, chan) (base + chan * 0x10)
/kernel/linux/linux-5.10/arch/xtensa/platforms/xtfpga/
H A Dsetup.c77 void __iomem *base = of_iomap(np, 0); in xtfpga_clk_setup() local
81 if (!base) { in xtfpga_clk_setup()
86 freq = __raw_readl(base); in xtfpga_clk_setup()
87 iounmap(base); in xtfpga_clk_setup()
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h44 #define LOONGSON3_REG8(base, x) \
45 (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
47 #define LOONGSON3_REG32(base, x) \
48 (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
194 /* PCI prefetch window base & mask */
/kernel/linux/linux-5.10/arch/parisc/boot/compressed/
H A Dmisc.c154 static int print_num(unsigned long num, int base) in print_num() argument
162 str[i--] = hex[num % base]; in print_num()
163 num = num / base; in print_num()
166 if (base == 16) { in print_num()

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