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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Danx9805.c24 #define anx9805_pad(p) container_of((p), struct anx9805_pad, base)
25 #define anx9805_bus(p) container_of((p), struct anx9805_bus, base)
26 #define anx9805_aux(p) container_of((p), struct anx9805_aux, base)
31 struct nvkm_i2c_pad base; member
37 struct nvkm_i2c_bus base; member
43 anx9805_bus_xfer(struct nvkm_i2c_bus *base, struct i2c_msg *msgs, int num) in anx9805_bus_xfer() argument
45 struct anx9805_bus *bus = anx9805_bus(base); in anx9805_bus_xfer()
103 anx9805_bus_new(struct nvkm_i2c_pad *base, int id, u8 drive, in anx9805_bus_new() argument
106 struct anx9805_pad *pad = anx9805_pad(base); in anx9805_bus_new()
112 *pbus = &bus->base; in anx9805_bus_new()
130 struct nvkm_i2c_aux base; global() member
136 anx9805_aux_xfer(struct nvkm_i2c_aux *base, bool retry, u8 type, u32 addr, u8 *data, u8 *size) anx9805_aux_xfer() argument
192 anx9805_aux_lnk_ctl(struct nvkm_i2c_aux *base, int link_nr, int link_bw, bool enh) anx9805_aux_lnk_ctl() argument
232 anx9805_aux_new(struct nvkm_i2c_pad *base, int id, u8 drive, struct nvkm_i2c_aux **pbus) anx9805_aux_new() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dnv50.c32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush() argument
34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush()
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm() argument
49 return nv50_bar(base)->bar1_vmm; in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait() argument
55 nvkm_bar_flush(base); in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init() argument
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) nv50_bar_bar2_vmm() argument
85 nv50_bar_bar2_init(struct nvkm_bar *base) nv50_bar_bar2_init() argument
95 nv50_bar_init(struct nvkm_bar *base) nv50_bar_init() argument
106 nv50_bar_oneinit(struct nvkm_bar *base) nv50_bar_oneinit() argument
204 nv50_bar_dtor(struct nvkm_bar *base) nv50_bar_dtor() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dnv50.c32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush() argument
34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush()
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm() argument
49 return nv50_bar(base)->bar1_vmm; in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait() argument
55 nvkm_bar_flush(base); in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init() argument
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) nv50_bar_bar2_vmm() argument
85 nv50_bar_bar2_init(struct nvkm_bar *base) nv50_bar_bar2_init() argument
95 nv50_bar_init(struct nvkm_bar *base) nv50_bar_init() argument
106 nv50_bar_oneinit(struct nvkm_bar *base) nv50_bar_oneinit() argument
204 nv50_bar_dtor(struct nvkm_bar *base) nv50_bar_dtor() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Danx9805.c24 #define anx9805_pad(p) container_of((p), struct anx9805_pad, base)
25 #define anx9805_bus(p) container_of((p), struct anx9805_bus, base)
26 #define anx9805_aux(p) container_of((p), struct anx9805_aux, base)
31 struct nvkm_i2c_pad base; member
37 struct nvkm_i2c_bus base; member
43 anx9805_bus_xfer(struct nvkm_i2c_bus *base, struct i2c_msg *msgs, int num) in anx9805_bus_xfer() argument
45 struct anx9805_bus *bus = anx9805_bus(base); in anx9805_bus_xfer()
103 anx9805_bus_new(struct nvkm_i2c_pad *base, int id, u8 drive, in anx9805_bus_new() argument
106 struct anx9805_pad *pad = anx9805_pad(base); in anx9805_bus_new()
112 *pbus = &bus->base; in anx9805_bus_new()
130 struct nvkm_i2c_aux base; global() member
136 anx9805_aux_xfer(struct nvkm_i2c_aux *base, bool retry, u8 type, u32 addr, u8 *data, u8 *size) anx9805_aux_xfer() argument
192 anx9805_aux_lnk_ctl(struct nvkm_i2c_aux *base, int link_nr, int link_bw, bool enh) anx9805_aux_lnk_ctl() argument
232 anx9805_aux_new(struct nvkm_i2c_pad *base, int id, u8 drive, struct nvkm_i2c_aux **pbus) anx9805_aux_new() argument
[all...]
/kernel/linux/linux-5.10/drivers/usb/chipidea/
H A Dusbmisc_imx.c156 void __iomem *base; member
175 val = readl(usbmisc->base); in usbmisc_imx25_init()
187 writel(val, usbmisc->base); in usbmisc_imx25_init()
190 val = readl(usbmisc->base); in usbmisc_imx25_init()
203 writel(val, usbmisc->base); in usbmisc_imx25_init()
226 reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET; in usbmisc_imx25_post()
263 val = readl(usbmisc->base) | val; in usbmisc_imx27_init()
265 val = readl(usbmisc->base) & ~val; in usbmisc_imx27_init()
266 writel(val, usbmisc->base); in usbmisc_imx27_init()
283 val = readl(usbmisc->base in usbmisc_imx53_init()
[all...]
/kernel/linux/linux-6.6/drivers/mmc/host/
H A Dsunplus-mmc.c164 void __iomem *base; member
180 return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state, in spmmc_wait_finish()
189 return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status, in spmmc_wait_sdstatus()
207 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); in spmmc_get_rsp()
208 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; in spmmc_get_rsp()
211 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); in spmmc_get_rsp()
212 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; in spmmc_get_rsp()
216 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG); in spmmc_get_rsp()
217 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; in spmmc_get_rsp()
224 value0_3 = readl(host->base in spmmc_get_rsp()
[all...]
/third_party/mesa3d/src/glx/
H A Ddrisw_glx.c143 __GLXDRIdrawable *pdraw = &(pdp->base); in swrastGetDrawableInfo()
186 __GLXDRIdrawable *pdraw = &(pdp->base); in swrastXPutImage()
277 __GLXDRIdrawable *pread = &(prp->base); in swrastGetImage2()
314 __GLXDRIdrawable *pread = &(prp->base); in swrastGetImageShm2()
347 .base = {__DRI_SWRAST_LOADER, 6 },
361 .base = {__DRI_SWRAST_LOADER, 3 },
383 .base = { __DRI_KOPPER_LOADER, 1 },
389 &swrastLoaderExtension_shm.base,
390 &kopperLoaderExtension.base,
395 &swrastLoaderExtension.base,
479 drisw_bind_tex_image(__GLXDRIdrawable *base, int buffer, const int *attrib_list) drisw_bind_tex_image() argument
509 drisw_release_tex_image(__GLXDRIdrawable *base, int buffer) drisw_release_tex_image() argument
554 drisw_create_context_attribs(struct glx_screen *base, struct glx_config *config_base, struct glx_context *shareList, unsigned num_attribs, const uint32_t *attribs, unsigned *error) drisw_create_context_attribs() argument
672 driswCreateDrawable(struct glx_screen *base, XID xDrawable, GLXDrawable drawable, int type, struct glx_config *modes) driswCreateDrawable() argument
783 driswDestroyScreen(struct glx_screen *base) driswDestroyScreen() argument
[all...]
/third_party/mesa3d/src/gallium/drivers/tegra/
H A Dtegra_context.c41 if (context->base.stream_uploader) in tegra_destroy()
42 u_upload_destroy(context->base.stream_uploader); in tegra_destroy()
851 view->base = *template; in tegra_create_sampler_view()
852 view->base.context = pcontext; in tegra_create_sampler_view()
854 view->base.texture = NULL; in tegra_create_sampler_view()
855 pipe_reference_init(&view->base.reference, 1); in tegra_create_sampler_view()
856 pipe_resource_reference(&view->base.texture, presource); in tegra_create_sampler_view()
865 return &view->base; in tegra_create_sampler_view()
874 pipe_resource_reference(&view->base.texture, NULL); in tegra_sampler_view_destroy()
901 memcpy(&surface->base, surfac in tegra_create_surface()
[all...]
/kernel/linux/linux-6.6/drivers/pmdomain/ti/
H A Domap_prm.c54 u32 base; member
68 void __iomem *base; member
157 .name = "mpu", .base = 0x4a306300,
161 .name = "tesla", .base = 0x4a306400,
166 .name = "abe", .base = 0x4a306500,
170 .name = "always_on_core", .base = 0x4a306600,
174 .name = "core", .base = 0x4a306700,
181 .name = "ivahd", .base = 0x4a306f00,
186 .name = "cam", .base = 0x4a307000,
190 .name = "dss", .base
[all...]
/kernel/linux/linux-6.6/drivers/media/platform/qcom/camss/
H A Dcamss-vfe-4-8.c252 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); in vfe_hw_version()
261 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_clr()
263 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
268 u32 bits = readl_relaxed(vfe->base + reg); in vfe_reg_set()
270 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
286 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); in vfe_global_reset()
290 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
296 vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_request()
301 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
385 writel_relaxed(reg, vfe->base in vfe_wm_line_based()
[all...]
/kernel/linux/linux-5.10/arch/x86/kernel/cpu/mtrr/
H A Dif.c38 mtrr_file_add(unsigned long base, unsigned long size, in mtrr_file_add() argument
52 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) in mtrr_file_add()
54 base >>= PAGE_SHIFT; in mtrr_file_add()
57 reg = mtrr_add_page(base, size, type, true); in mtrr_file_add()
64 mtrr_file_del(unsigned long base, unsigned long size, in mtrr_file_del() argument
71 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) in mtrr_file_del()
73 base >>= PAGE_SHIFT; in mtrr_file_del()
76 reg = mtrr_del_page(-1, base, size); in mtrr_file_del()
91 * "base=%Lx size=%Lx type=%s" or "disable=%d"
98 unsigned long long base, siz in mtrr_write() local
159 unsigned long base; mtrr_ioctl() local
362 unsigned long base, size; mtrr_seq_show() local
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-fttmr010.c100 void __iomem *base; member
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
129 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down()
156 writel(cycles, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_next_event()
159 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
176 writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR); in ast2600_timer_shutdown()
187 cr = readl(fttmr010->base in fttmr010_timer_shutdown()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/mxsfb/
H A Dmxsfb_kms.c66 ctrl1 = readl(mxsfb->base + LCDC_CTRL1); in mxsfb_set_formats()
98 writel(ctrl1, mxsfb->base + LCDC_CTRL1); in mxsfb_set_formats()
99 writel(ctrl, mxsfb->base + LCDC_CTRL); in mxsfb_set_formats()
112 reg = readl(mxsfb->base + LCDC_V4_CTRL2); in mxsfb_enable_controller()
115 writel(reg, mxsfb->base + LCDC_V4_CTRL2); in mxsfb_enable_controller()
119 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
122 reg = readl(mxsfb->base + LCDC_VDCTRL4); in mxsfb_enable_controller()
124 writel(reg, mxsfb->base + LCDC_VDCTRL4); in mxsfb_enable_controller()
151 reg = readl(mxsfb->base + LCDC_CTRL1); in mxsfb_enable_controller()
153 writel(reg, mxsfb->base in mxsfb_enable_controller()
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-fttmr010.c100 void __iomem *base; member
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
129 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down()
156 writel(cycles, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_next_event()
159 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
176 writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR); in ast2600_timer_shutdown()
187 cr = readl(fttmr010->base in fttmr010_timer_shutdown()
[all...]
/kernel/linux/linux-6.6/arch/x86/kernel/cpu/mtrr/
H A Dif.c38 mtrr_file_add(unsigned long base, unsigned long size, in mtrr_file_add() argument
52 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) in mtrr_file_add()
54 base >>= PAGE_SHIFT; in mtrr_file_add()
57 reg = mtrr_add_page(base, size, type, true); in mtrr_file_add()
64 mtrr_file_del(unsigned long base, unsigned long size, in mtrr_file_del() argument
71 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) in mtrr_file_del()
73 base >>= PAGE_SHIFT; in mtrr_file_del()
76 reg = mtrr_del_page(-1, base, size); in mtrr_file_del()
91 * "base=%Lx size=%Lx type=%s" or "disable=%d"
98 unsigned long long base, siz in mtrr_write() local
159 unsigned long base; mtrr_ioctl() local
362 unsigned long base, size; mtrr_seq_show() local
[all...]
/third_party/backends/sanei/
H A Dsanei_ab306.c83 u_long base; /* i/o base address */ member
150 u_long base = p->base; in ab306_cout() local
152 while ((ab306_inb (p, base + 1) & 0x80)); /* wait for dir flag */ in ab306_cout()
153 ab306_outb (p, base, val); in ab306_cout()
154 ab306_outb (p, base + 1, 0xe0); in ab306_cout()
155 while ((ab306_inb (p, base + 1) & 0x80) == 0); /* wait for ack */ in ab306_cout()
156 ab306_outb (p, base + 1, 0x60); in ab306_cout()
163 u_long base in ab306_cin() local
177 u_long base = p->base; ab306_write() local
230 u_long base; sanei_ab306_open() local
[all...]
/kernel/linux/linux-6.6/include/crypto/internal/
H A Daead.h22 char head[offsetof(struct aead_alg, base)];
23 struct crypto_instance base; member
30 struct crypto_spawn base; member
34 struct crypto_queue base; member
39 return crypto_tfm_ctx(&tfm->base); in crypto_aead_ctx()
44 return crypto_tfm_ctx_dma(&tfm->base); in crypto_aead_ctx_dma()
50 return container_of(&inst->alg.base, struct crypto_instance, alg); in aead_crypto_instance()
55 return container_of(&inst->alg, struct aead_instance, alg.base); in aead_instance()
60 return aead_instance(crypto_tfm_alg_instance(&aead->base)); in aead_alg_instance()
85 crypto_request_complete(&req->base, er in aead_request_complete()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dspp.c29 u32 base; in dpu_setup_dspp_pcc() local
36 base = ctx->cap->sblk->pcc.base; in dpu_setup_dspp_pcc()
38 if (!base) { in dpu_setup_dspp_pcc()
39 DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base); in dpu_setup_dspp_pcc()
45 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); in dpu_setup_dspp_pcc()
49 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); in dpu_setup_dspp_pcc()
50 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); in dpu_setup_dspp_pcc()
51 DPU_REG_WRITE(&ctx->hw, base in dpu_setup_dspp_pcc()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_simple_resource.c34 * @base: The TTM base object implementing user-space visibility.
38 struct ttm_base_object base; member
100 ttm_base_object_kfree(usimple, base); in vmw_simple_resource_free()
114 struct ttm_base_object *base = *p_base; in vmw_simple_resource_base_release() local
116 container_of(base, struct vmw_user_simple_resource, base); in vmw_simple_resource_base_release()
161 usimple->base.shareable = false; in vmw_simple_resource_create_ioctl()
162 usimple->base.tfile = NULL; in vmw_simple_resource_create_ioctl()
173 ret = ttm_base_object_init(tfile, &usimple->base, fals in vmw_simple_resource_create_ioctl()
207 struct ttm_base_object *base; vmw_simple_resource_lookup() local
[all...]
/third_party/node/deps/zlib/google/
H A Dcompression_utils.cc7 #include "base/check_op.h"
8 #include "base/process/memory.h"
9 #include "base/sys_byteorder.h"
15 bool GzipCompress(base::span<const char> input, in GzipCompress()
36 bool GzipCompress(base::span<const char> input, std::string* output) { in GzipCompress()
37 return GzipCompress(base::as_bytes(input), output); in GzipCompress()
40 bool GzipCompress(base::span<const uint8_t> input, std::string* output) { in GzipCompress()
50 if (!base::UncheckedMalloc(compressed_data_size, in GzipCompress()
93 bool GzipUncompress(base::span<const char> input, in GzipUncompress()
94 base in GzipUncompress()
[all...]
/third_party/vulkan-headers/include/vulkan/
H A Dvk_icd.h130 VkIcdSurfaceBase base; member
138 VkIcdSurfaceBase base; member
146 VkIcdSurfaceBase base; member
154 VkIcdSurfaceBase base; member
162 VkIcdSurfaceBase base; member
170 VkIcdSurfaceBase base; member
178 VkIcdSurfaceBase base; member
185 VkIcdSurfaceBase base; member
192 VkIcdSurfaceBase base; member
199 VkIcdSurfaceBase base; member
205 VkIcdSurfaceBase base; global() member
216 VkIcdSurfaceBase base; global() member
221 VkIcdSurfaceBase base; global() member
228 VkIcdSurfaceBase base; global() member
235 VkIcdSurfaceBase base; global() member
243 VkIcdSurfaceBase base; global() member
249 VkIcdSurfaceBase base; global() member
[all...]
/kernel/linux/linux-5.10/arch/mips/ath25/
H A Dearly_printk.c18 static inline void prom_uart_wr(void __iomem *base, unsigned reg, in prom_uart_wr() argument
21 __raw_writel(ch, base + 4 * reg); in prom_uart_wr()
24 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) in prom_uart_rr() argument
26 return __raw_readl(base + 4 * reg); in prom_uart_rr()
31 static void __iomem *base; in prom_putchar() local
33 if (unlikely(base == NULL)) { in prom_putchar()
35 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); in prom_putchar()
37 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); in prom_putchar()
40 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) in prom_putchar()
42 prom_uart_wr(base, UART_T in prom_putchar()
[all...]
/kernel/linux/linux-6.6/arch/mips/ath25/
H A Dearly_printk.c18 static inline void prom_uart_wr(void __iomem *base, unsigned reg, in prom_uart_wr() argument
21 __raw_writel(ch, base + 4 * reg); in prom_uart_wr()
24 static inline unsigned char prom_uart_rr(void __iomem *base, unsigned reg) in prom_uart_rr() argument
26 return __raw_readl(base + 4 * reg); in prom_uart_rr()
31 static void __iomem *base; in prom_putchar() local
33 if (unlikely(base == NULL)) { in prom_putchar()
35 base = (void __iomem *)(KSEG1ADDR(AR2315_UART0_BASE)); in prom_putchar()
37 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); in prom_putchar()
40 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) in prom_putchar()
42 prom_uart_wr(base, UART_T in prom_putchar()
[all...]
/kernel/linux/linux-5.10/drivers/clk/davinci/
H A Dpll-da850.c89 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll0_init() argument
93 davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); in da850_pll0_init()
95 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); in da850_pll0_init()
98 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); in da850_pll0_init()
103 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); in da850_pll0_init()
106 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); in da850_pll0_init()
110 davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); in da850_pll0_init()
112 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); in da850_pll0_init()
115 davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); in da850_pll0_init()
117 davinci_pll_auxclk_register(dev, "pll0_auxclk", base); in da850_pll0_init()
144 void __iomem *base; of_da850_pll0_init() local
198 da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) da850_pll1_init() argument
223 of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) of_da850_pll1_init() argument
[all...]
/kernel/linux/linux-6.6/drivers/clk/davinci/
H A Dpll-da850.c89 int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) in da850_pll0_init() argument
93 davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip); in da850_pll0_init()
95 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base); in da850_pll0_init()
98 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base); in da850_pll0_init()
103 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base); in da850_pll0_init()
106 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base); in da850_pll0_init()
110 davinci_pll_sysclk_register(dev, &pll0_sysclk5, base); in da850_pll0_init()
112 clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base); in da850_pll0_init()
115 davinci_pll_sysclk_register(dev, &pll0_sysclk7, base); in da850_pll0_init()
117 davinci_pll_auxclk_register(dev, "pll0_auxclk", base); in da850_pll0_init()
144 void __iomem *base; of_da850_pll0_init() local
198 da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) da850_pll1_init() argument
223 of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip) of_da850_pll1_init() argument
[all...]

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