Lines Matching refs:base
164 void __iomem *base;
180 return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state,
189 return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status,
207 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
208 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
211 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
212 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
216 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
217 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
224 value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
225 value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
236 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
248 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
253 u32 value = readl(host->base + SPMMC_SD_CONFIG1_REG);
254 int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG));
282 writel(value, host->base + SPMMC_SD_CONFIG1_REG);
283 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
288 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
291 writel(value, host->base + SPMMC_SD_CONFIG1_REG);
294 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
296 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
298 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
300 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
306 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
322 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
330 u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
334 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
346 value = readl(host->base + SPMMC_HW_DMA_CTRL_REG);
348 writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
350 writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
351 value = readl(host->base + SPMMC_HW_DMA_CTRL_REG);
353 writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
354 writel(0x7, host->base + SPMMC_SD_RST_REG);
355 readl_poll_timeout_atomic(host->base + SPMMC_SD_HW_STATE_REG, value,
365 writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG);
366 writeb(cmd->arg & 0xff, host->base + SPMMC_SD_CMDBUF4_REG);
369 value = readl(host->base + SPMMC_SD_INT_REG);
372 writel(value, host->base + SPMMC_SD_INT_REG);
374 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
381 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
398 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
405 writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG);
406 writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG);
407 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
413 srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
418 writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
422 srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
427 writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
448 writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG);
449 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG);
451 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG);
452 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_1_LENG_REG);
454 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_2_ADDR_REG);
455 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_2_LENG_REG);
457 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_3_ADDR_REG);
458 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_3_LENG_REG);
460 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_4_ADDR_REG);
461 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_4_LENG_REG);
463 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_5_ADDR_REG);
464 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_5_LENG_REG);
466 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_6_ADDR_REG);
467 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_6_LENG_REG);
469 writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_7_ADDR_REG);
470 writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_7_LENG_REG);
474 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
478 value = readl(host->base + SPMMC_SD_INT_REG);
481 writel(value, host->base + SPMMC_SD_INT_REG);
486 writel(value, host->base + SPMMC_SD_CONFIG0_REG);
492 u32 value = readl(host->base + SPMMC_SD_CTRL_REG);
495 writel(value, host->base + SPMMC_SD_CTRL_REG);
507 value = readl(host->base + SPMMC_SD_INT_REG);
510 writel(value, host->base + SPMMC_SD_INT_REG);
512 readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, value,
522 u32 value = readl(host->base + SPMMC_SD_STATE_REG);
528 value = readl(host->base + SPMMC_SD_STATUS_REG);
531 timing_cfg0 = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
593 writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
648 writel(*buf, host->base + SPMMC_SD_PIODATATX_REG);
652 *buf = readl(host->base + SPMMC_SD_PIODATARX_REG);
676 value = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
679 writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
716 u32 value = readl(host->base + SPMMC_SD_INT_REG);
721 writel(value, host->base + SPMMC_SD_INT_REG);
753 value = readl(host->base + SPMMC_SD_INT_REG);
755 writel(value, host->base + SPMMC_SD_INT_REG);
811 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
818 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
829 value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
836 writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
875 host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
876 if (IS_ERR(host->base))
877 return PTR_ERR(host->base);