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/third_party/typescript/tests/baselines/reference/
H A DdivergentAccessorsVisibility1.js97 declare const base: Base, deriv: Derived;
99 base.PublicPublic = 0;
100 base.PublicProtected = 0;
101 base.PublicPrivate = 0;
102 base.ProtectedPublic = 0;
103 base.ProtectedProtected = 0;
104 base.ProtectedPrivate = 0;
105 base.PrivatePublic = 0;
106 base.PrivateProtected = 0;
107 base
[all...]
/kernel/linux/linux-5.10/arch/loongarch/kernel/
H A Dfpu.S51 .macro sc_save_fp base
52 EX fst.d $f0, \base, (0 * FPU_REG_WIDTH)
53 EX fst.d $f1, \base, (1 * FPU_REG_WIDTH)
54 EX fst.d $f2, \base, (2 * FPU_REG_WIDTH)
55 EX fst.d $f3, \base, (3 * FPU_REG_WIDTH)
56 EX fst.d $f4, \base, (4 * FPU_REG_WIDTH)
57 EX fst.d $f5, \base, (5 * FPU_REG_WIDTH)
58 EX fst.d $f6, \base, (6 * FPU_REG_WIDTH)
59 EX fst.d $f7, \base, (7 * FPU_REG_WIDTH)
60 EX fst.d $f8, \base, (
[all...]
/kernel/linux/linux-6.6/drivers/crypto/starfive/
H A Djh7110-hash.c44 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, in starfive_hash_wait_busy()
53 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_HASH_SHACSR, status, in starfive_hash_wait_key_done()
65 writel(ctx->keylen, cryp->base + STARFIVE_HASH_SHAWKLEN); in starfive_hash_hmac_key()
70 writel(rctx->csr.hash.v, cryp->base + STARFIVE_HASH_SHACSR); in starfive_hash_hmac_key()
73 writel(*key, cryp->base + STARFIVE_HASH_SHAWKR); in starfive_hash_hmac_key()
78 writeb(*cl, cryp->base + STARFIVE_HASH_SHAWKR); in starfive_hash_hmac_key()
101 writel(alg_cr.v, cryp->base + STARFIVE_ALG_CR_OFFSET); in starfive_hash_start()
103 csr.v = readl(cryp->base + STARFIVE_HASH_SHACSR); in starfive_hash_start()
107 stat = readl(cryp->base + STARFIVE_IE_MASK_OFFSET); in starfive_hash_start()
109 writel(stat, cryp->base in starfive_hash_start()
[all...]
/base/security/crypto_framework/test/unittest/src/ecc/
H A Decc_asy_key_common.cpp40 eccCommSpec->base.algName = const_cast<char *>(g_eccAlgName.c_str()); in ConstructEcc192CommParamsSpec()
41 eccCommSpec->base.specType = HCF_COMMON_PARAMS_SPEC; in ConstructEcc192CommParamsSpec()
68 eccCommSpec->base.algName = const_cast<char *>(g_eccAlgName.c_str()); in ConstructEcc224CommParamsSpec()
69 eccCommSpec->base.specType = HCF_COMMON_PARAMS_SPEC; in ConstructEcc224CommParamsSpec()
96 eccPubKeySpec->base.base.algName = const_cast<char *>(g_eccAlgName.c_str()); in ConstructEcc224PubKeyParamsSpec()
97 eccPubKeySpec->base.base.specType = HCF_PUBLIC_KEY_SPEC; in ConstructEcc224PubKeyParamsSpec()
98 eccPubKeySpec->base.field = tmpField; in ConstructEcc224PubKeyParamsSpec()
99 eccPubKeySpec->base in ConstructEcc224PubKeyParamsSpec()
[all...]
/kernel/linux/linux-5.10/arch/loongarch/lib/
H A Dxor_simd.c19 #define LD(reg, base, offset) \
20 "vld $vr" #reg ", %[" #base "], " #offset "\n\t"
21 #define ST(reg, base, offset) \
22 "vst $vr" #reg ", %[" #base "], " #offset "\n\t"
25 #define LD_INOUT_LINE(base) \
26 LD(0, base, 0) \
27 LD(1, base, 16) \
28 LD(2, base, 32) \
29 LD(3, base, 48)
31 #define LD_AND_XOR_LINE(base) \
[all...]
/kernel/linux/linux-6.6/arch/loongarch/lib/
H A Dxor_simd.c19 #define LD(reg, base, offset) \
20 "vld $vr" #reg ", %[" #base "], " #offset "\n\t"
21 #define ST(reg, base, offset) \
22 "vst $vr" #reg ", %[" #base "], " #offset "\n\t"
25 #define LD_INOUT_LINE(base) \
26 LD(0, base, 0) \
27 LD(1, base, 16) \
28 LD(2, base, 32) \
29 LD(3, base, 48)
31 #define LD_AND_XOR_LINE(base) \
[all...]
/kernel/linux/linux-5.10/drivers/s390/block/
H A Ddasd_ioctl.c47 struct dasd_device *base; in dasd_ioctl_enable() local
52 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable()
53 if (!base) in dasd_ioctl_enable()
56 dasd_enable_device(base); in dasd_ioctl_enable()
58 bd_set_nr_sectors(bdev, get_capacity(base->block->gdp)); in dasd_ioctl_enable()
59 dasd_put_device(base); in dasd_ioctl_enable()
70 struct dasd_device *base; in dasd_ioctl_disable() local
75 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable()
76 if (!base) in dasd_ioctl_disable()
86 dasd_set_target_state(base, DASD_STATE_BASI in dasd_ioctl_disable()
102 struct dasd_device *base; dasd_ioctl_quiesce() local
123 struct dasd_device *base; dasd_ioctl_resume() local
146 struct dasd_device *base; dasd_ioctl_abortio() local
181 struct dasd_device *base; dasd_ioctl_allowio() local
202 struct dasd_device *base; dasd_format() local
241 struct dasd_device *base; dasd_check_format() local
261 struct dasd_device *base; dasd_ioctl_format() local
299 struct dasd_device *base; dasd_ioctl_check_format() local
350 struct dasd_device *base; dasd_ioctl_release_space() local
462 struct dasd_device *base; __dasd_ioctl_information() local
539 struct dasd_device *base; dasd_ioctl_set_ro() local
579 struct dasd_device *base; dasd_ioctl() local
682 struct dasd_device *base; dasd_biodasdinfo() local
[all...]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
H A Dppc_asm.h77 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
78 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
79 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
80 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
[all...]
/kernel/linux/linux-5.10/tools/testing/selftests/powerpc/primitives/asm/
H A Dppc_asm.h77 #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
78 #define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
79 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
80 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c12 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing() local
14 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
29 dsi_phy_write(base in dsi_20nm_dphy_set_timing()
44 void __iomem *base = phy->reg_base; dsi_20nm_phy_regulator_ctrl() local
71 void __iomem *base = phy->base; dsi_20nm_phy_enable() local
[all...]
/kernel/linux/linux-6.6/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt2701.c53 void __iomem *base = hdmi_phy->regs; in mtk_hdmi_pll_prepare() local
55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); in mtk_hdmi_pll_prepare()
56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); in mtk_hdmi_pll_prepare()
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); in mtk_hdmi_pll_prepare()
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); in mtk_hdmi_pll_prepare()
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); in mtk_hdmi_pll_prepare()
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); in mtk_hdmi_pll_prepare()
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); in mtk_hdmi_pll_prepare()
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); in mtk_hdmi_pll_prepare()
65 mtk_phy_set_bits(base in mtk_hdmi_pll_prepare()
75 void __iomem *base = hdmi_phy->regs; mtk_hdmi_pll_unprepare() local
103 void __iomem *base = hdmi_phy->regs; mtk_hdmi_pll_set_rate() local
179 void __iomem *base = hdmi_phy->regs; mtk_hdmi_phy_enable_tmds() local
199 void __iomem *base = hdmi_phy->regs; mtk_hdmi_phy_disable_tmds() local
[all...]
/kernel/linux/linux-6.6/drivers/s390/block/
H A Ddasd_ioctl.c47 struct dasd_device *base; in dasd_ioctl_enable() local
52 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable()
53 if (!base) in dasd_ioctl_enable()
56 dasd_enable_device(base); in dasd_ioctl_enable()
57 dasd_put_device(base); in dasd_ioctl_enable()
68 struct dasd_device *base; in dasd_ioctl_disable() local
73 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable()
74 if (!base) in dasd_ioctl_disable()
84 dasd_set_target_state(base, DASD_STATE_BASIC); in dasd_ioctl_disable()
90 dasd_put_device(base); in dasd_ioctl_disable()
100 struct dasd_device *base; dasd_ioctl_quiesce() local
121 struct dasd_device *base; dasd_ioctl_resume() local
144 struct dasd_device *base; dasd_ioctl_abortio() local
179 struct dasd_device *base; dasd_ioctl_allowio() local
200 struct dasd_device *base; dasd_format() local
238 struct dasd_device *base; dasd_check_format() local
258 struct dasd_device *base; dasd_ioctl_format() local
296 struct dasd_device *base; dasd_ioctl_check_format() local
347 struct dasd_device *base; dasd_ioctl_release_space() local
509 struct dasd_device *base; __dasd_ioctl_information() local
585 struct dasd_device *base; dasd_set_read_only() local
620 struct dasd_device *base; dasd_ioctl() local
721 struct dasd_device *base; dasd_biodasdinfo() local
[all...]
/kernel/linux/linux-5.10/include/linux/
H A Dkstrtox.h9 int __must_check _kstrtoul(const char *s, unsigned int base, unsigned long *res);
10 int __must_check _kstrtol(const char *s, unsigned int base, long *res);
12 int __must_check kstrtoull(const char *s, unsigned int base, unsigned long long *res);
13 int __must_check kstrtoll(const char *s, unsigned int base, long long *res);
20 * @base: The number base to use. The maximum supported base is 16. If base is
21 * given as 0, then the base of the string is automatically detected with the
30 static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigne argument
58 kstrtol(const char *s, unsigned int base, long *res) kstrtol() argument
74 kstrtou64(const char *s, unsigned int base, u64 *res) kstrtou64() argument
79 kstrtos64(const char *s, unsigned int base, s64 *res) kstrtos64() argument
84 kstrtou32(const char *s, unsigned int base, u32 *res) kstrtou32() argument
89 kstrtos32(const char *s, unsigned int base, s32 *res) kstrtos32() argument
112 kstrtou64_from_user(const char __user *s, size_t count, unsigned int base, u64 *res) kstrtou64_from_user() argument
117 kstrtos64_from_user(const char __user *s, size_t count, unsigned int base, s64 *res) kstrtos64_from_user() argument
122 kstrtou32_from_user(const char __user *s, size_t count, unsigned int base, u32 *res) kstrtou32_from_user() argument
127 kstrtos32_from_user(const char __user *s, size_t count, unsigned int base, s32 *res) kstrtos32_from_user() argument
[all...]
/kernel/linux/linux-6.6/include/linux/
H A Dkstrtox.h9 int __must_check _kstrtoul(const char *s, unsigned int base, unsigned long *res);
10 int __must_check _kstrtol(const char *s, unsigned int base, long *res);
12 int __must_check kstrtoull(const char *s, unsigned int base, unsigned long long *res);
13 int __must_check kstrtoll(const char *s, unsigned int base, long long *res);
20 * @base: The number base to use. The maximum supported base is 16. If base is
21 * given as 0, then the base of the string is automatically detected with the
30 static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigne argument
58 kstrtol(const char *s, unsigned int base, long *res) kstrtol() argument
74 kstrtou64(const char *s, unsigned int base, u64 *res) kstrtou64() argument
79 kstrtos64(const char *s, unsigned int base, s64 *res) kstrtos64() argument
84 kstrtou32(const char *s, unsigned int base, u32 *res) kstrtou32() argument
89 kstrtos32(const char *s, unsigned int base, s32 *res) kstrtos32() argument
112 kstrtou64_from_user(const char __user *s, size_t count, unsigned int base, u64 *res) kstrtou64_from_user() argument
117 kstrtos64_from_user(const char __user *s, size_t count, unsigned int base, s64 *res) kstrtos64_from_user() argument
122 kstrtou32_from_user(const char __user *s, size_t count, unsigned int base, u32 *res) kstrtou32_from_user() argument
127 kstrtos32_from_user(const char __user *s, size_t count, unsigned int base, s32 *res) kstrtos32_from_user() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-winbond.c131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter() argument
144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME)) in winbond_sio_enter()
151 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
152 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical() argument
159 outb(WB_SIO_REG_LOGICAL, base); in winbond_sio_select_logical()
160 outb(dev, base + 1); in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave() argument
165 outb(WB_SIO_EXT_EXIT_KEY, base); in winbond_sio_leave()
170 winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) winbond_sio_reg_write() argument
176 winbond_sio_reg_read(unsigned long base, u8 reg) winbond_sio_reg_read() argument
182 winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) winbond_sio_reg_bset() argument
191 winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) winbond_sio_reg_bclear() argument
200 winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) winbond_sio_reg_btest() argument
385 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_get() local
409 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_direction_in() local
433 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_direction_out() local
464 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_set() local
497 winbond_gpio_configure_port0_pins(unsigned long base) winbond_gpio_configure_port0_pins() argument
514 winbond_gpio_configure_port1_check_i2c(unsigned long base) winbond_gpio_configure_port1_check_i2c() argument
522 winbond_gpio_configure_port(unsigned long base, unsigned int idx) winbond_gpio_configure_port() argument
571 winbond_gpio_configure(unsigned long base) winbond_gpio_configure() argument
587 winbond_gpio_check_chip(unsigned long base) winbond_gpio_check_chip() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-winbond.c131 unsigned long base; member
142 static int winbond_sio_enter(unsigned long base) in winbond_sio_enter() argument
144 if (!request_muxed_region(base, 2, WB_GPIO_DRIVER_NAME)) in winbond_sio_enter()
151 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
152 outb(WB_SIO_EXT_ENTER_KEY, base); in winbond_sio_enter()
157 static void winbond_sio_select_logical(unsigned long base, u8 dev) in winbond_sio_select_logical() argument
159 outb(WB_SIO_REG_LOGICAL, base); in winbond_sio_select_logical()
160 outb(dev, base + 1); in winbond_sio_select_logical()
163 static void winbond_sio_leave(unsigned long base) in winbond_sio_leave() argument
165 outb(WB_SIO_EXT_EXIT_KEY, base); in winbond_sio_leave()
170 winbond_sio_reg_write(unsigned long base, u8 reg, u8 data) winbond_sio_reg_write() argument
176 winbond_sio_reg_read(unsigned long base, u8 reg) winbond_sio_reg_read() argument
182 winbond_sio_reg_bset(unsigned long base, u8 reg, u8 bit) winbond_sio_reg_bset() argument
191 winbond_sio_reg_bclear(unsigned long base, u8 reg, u8 bit) winbond_sio_reg_bclear() argument
200 winbond_sio_reg_btest(unsigned long base, u8 reg, u8 bit) winbond_sio_reg_btest() argument
385 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_get() local
409 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_direction_in() local
433 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_direction_out() local
464 unsigned long *base = gpiochip_get_data(gc); winbond_gpio_set() local
497 winbond_gpio_configure_port0_pins(unsigned long base) winbond_gpio_configure_port0_pins() argument
514 winbond_gpio_configure_port1_check_i2c(unsigned long base) winbond_gpio_configure_port1_check_i2c() argument
522 winbond_gpio_configure_port(unsigned long base, unsigned int idx) winbond_gpio_configure_port() argument
571 winbond_gpio_configure(unsigned long base) winbond_gpio_configure() argument
587 winbond_gpio_check_chip(unsigned long base) winbond_gpio_check_chip() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx6q.c434 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
456 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
457 WARN_ON(!base); in imx6q_clocks_init()
468 hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
469 hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
470 hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
471 hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
472 hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
473 hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
474 hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base in imx6q_clocks_init()
[all...]
H A Dclk-imx7ulp.c50 void __iomem *base; in imx7ulp_clk_scg1_init() local
69 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
70 WARN_ON(!base); in imx7ulp_clk_scg1_init()
73 hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
74 hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
77 hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
78 hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
80 /* name parent_name base */ in imx7ulp_clk_scg1_init()
81 hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4("apll", "apll_pre_div", base + 0x500); in imx7ulp_clk_scg1_init()
82 hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base in imx7ulp_clk_scg1_init()
139 void __iomem *base; imx7ulp_clk_pcc2_init() local
187 void __iomem *base; imx7ulp_clk_pcc3_init() local
234 void __iomem *base; imx7ulp_clk_smc1_init() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx6q.c439 void __iomem *anatop_base, *base; in imx6q_clocks_init() local
461 anatop_base = base = of_iomap(np, 0); in imx6q_clocks_init()
462 WARN_ON(!base); in imx6q_clocks_init()
473 hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
474 hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
475 hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
476 hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
477 hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
478 hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6q_clocks_init()
479 hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base in imx6q_clocks_init()
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H A Dclk-imx7ulp.c50 void __iomem *base; in imx7ulp_clk_scg1_init() local
69 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
70 WARN_ON(!base); in imx7ulp_clk_scg1_init()
73 hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
74 hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); in imx7ulp_clk_scg1_init()
77 hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
78 hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); in imx7ulp_clk_scg1_init()
80 /* name parent_name base */ in imx7ulp_clk_scg1_init()
81 hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500); in imx7ulp_clk_scg1_init()
82 hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base in imx7ulp_clk_scg1_init()
139 void __iomem *base; imx7ulp_clk_pcc2_init() local
187 void __iomem *base; imx7ulp_clk_pcc3_init() local
234 void __iomem *base; imx7ulp_clk_smc1_init() local
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/third_party/node/deps/v8/src/strings/
H A Dchar-predicates.h8 #include "src/base/strings.h"
18 inline constexpr int AsciiAlphaToLower(base::uc32 c);
19 inline constexpr bool IsCarriageReturn(base::uc32 c);
20 inline constexpr bool IsLineFeed(base::uc32 c);
21 inline constexpr bool IsAsciiIdentifier(base::uc32 c);
22 inline constexpr bool IsAlphaNumeric(base::uc32 c);
23 inline constexpr bool IsDecimalDigit(base::uc32 c);
24 inline constexpr bool IsHexDigit(base::uc32 c);
25 inline constexpr bool IsOctalDigit(base::uc32 c);
26 inline constexpr bool IsBinaryDigit(base
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/third_party/skia/third_party/externals/zlib/google/
H A Dzip.cc11 #include "base/bind.h"
12 #include "base/files/file.h"
13 #include "base/files/file_enumerator.h"
14 #include "base/logging.h"
15 #include "base/memory/ptr_util.h"
16 #include "base/strings/string_util.h"
25 bool IsHiddenFile(const base::FilePath& file_path) { in IsHiddenFile()
29 bool ExcludeNoFilesFilter(const base::FilePath& file_path) { in ExcludeNoFilesFilter()
33 bool ExcludeHiddenFilesFilter(const base::FilePath& file_path) { in ExcludeHiddenFilesFilter()
38 bool CreateDirectory(const base
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/kernel/linux/linux-6.6/arch/powerpc/include/asm/
H A Dppc_asm.h23 * op reg, (offset + (width * reg))(base)
28 .macro OP_REGS op, width, start, end, base, offset variable
31 \op .Lreg, \offset + \width * .Lreg(\base)
55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
58 #define REST_NVGPRS(base) REST_GPR
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm.c101 void __iomem *base = pll_28nm->phy->pll_base; in pll_28nm_software_reset() local
107 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, in pll_28nm_software_reset()
109 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
120 void __iomem *base = pll_28nm->phy->pll_base; in dsi_pll_28nm_clk_set_rate() local
131 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG, 3); in dsi_pll_28nm_clk_set_rate()
142 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFR_CFG, lpfr_lut[i].resistance); in dsi_pll_28nm_clk_set_rate()
145 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate()
146 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate()
171 sdm_cfg1 = dsi_phy_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG1); in dsi_pll_28nm_clk_set_rate()
198 dsi_phy_write(base in dsi_pll_28nm_clk_set_rate()
244 void __iomem *base = pll_28nm->phy->pll_base; dsi_pll_28nm_clk_recalc_rate() local
291 void __iomem *base = pll_28nm->phy->pll_base; _dsi_pll_28nm_vco_prepare_hpm() local
385 void __iomem *base = pll_28nm->phy->pll_base; dsi_pll_28nm_vco_prepare_8226() local
453 void __iomem *base = pll_28nm->phy->pll_base; dsi_pll_28nm_vco_prepare_lp() local
560 void __iomem *base = pll_28nm->phy->pll_base; dsi_28nm_pll_save_state() local
577 void __iomem *base = pll_28nm->phy->pll_base; dsi_28nm_pll_restore_state() local
701 void __iomem *base = phy->base; dsi_28nm_dphy_set_timing() local
733 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_enable_dcdc() local
748 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_enable_ldo() local
783 void __iomem *base = phy->base; dsi_28nm_phy_enable() local
[all...]
/kernel/linux/linux-6.6/tools/testing/selftests/powerpc/primitives/asm/
H A Dppc_asm.h23 * op reg, (offset + (width * reg))(base)
28 .macro OP_REGS op, width, start, end, base, offset variable
31 \op .Lreg, \offset + \width * .Lreg(\base)
55 #define SAVE_GPRS(start, end, base) OP_REGS std, 8, start, end, base, GPR0
56 #define REST_GPRS(start, end, base) OP_REGS ld, 8, start, end, base, GPR0
57 #define SAVE_NVGPRS(base) SAVE_GPRS(14, 31, base)
58 #define REST_NVGPRS(base) REST_GPR
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