Lines Matching refs:base
53 void __iomem *base = hdmi_phy->regs;
55 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
56 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
57 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
58 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
60 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
61 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
62 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
64 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
65 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
66 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
67 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
75 void __iomem *base = hdmi_phy->regs;
77 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
78 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
79 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
80 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
82 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
83 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
84 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
86 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
87 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
88 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
89 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
103 void __iomem *base = hdmi_phy->regs;
113 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);
114 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
115 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
116 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);
117 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);
118 mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div);
119 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);
120 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);
121 mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2);
122 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);
123 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);
124 mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);
126 mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP);
127 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3);
128 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
129 mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28);
130 mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);
131 mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);
179 void __iomem *base = hdmi_phy->regs;
181 mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
182 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
183 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
184 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
186 mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
187 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
188 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
190 mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
191 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
192 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
193 mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
199 void __iomem *base = hdmi_phy->regs;
201 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
202 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
203 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
204 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
206 mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
207 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
208 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
210 mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
211 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
212 mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
213 mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);