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/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
H A Dvc4_gem.c126 bo_state[i].paddr = vc4_bo->base.paddr; in vc4_get_hang_state_ioctl()
127 bo_state[i].size = vc4_bo->base.base.size; in vc4_get_hang_state_ioctl()
199 bo = to_vc4_bo(&exec[i]->bo[j]->base); in vc4_save_hang_state()
207 drm_gem_object_get(&exec[i]->bo[j]->base); in vc4_save_hang_state()
208 kernel_state->bo[k++] = &exec[i]->bo[j]->base; in vc4_save_hang_state()
215 drm_gem_object_get(&bo->base.base); in vc4_save_hang_state()
216 kernel_state->bo[k++] = &bo->base.base; in vc4_save_hang_state()
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/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/
H A Dhip04_eth.c210 void __iomem *base; member
284 writel_relaxed(val, priv->base + GE_PORT_MODE); in hip04_config_port()
287 writel_relaxed(val, priv->base + GE_DUPLEX_TYPE); in hip04_config_port()
290 writel_relaxed(val, priv->base + GE_MODE_CHANGE_REG); in hip04_config_port()
316 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE); in hip04_config_fifo()
318 writel_relaxed(val, priv->base + PPE_CFG_STS_MODE); in hip04_config_fifo()
325 writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN); in hip04_config_fifo()
336 writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG); in hip04_config_fifo()
339 writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG); in hip04_config_fifo()
342 writel_relaxed(val, priv->base in hip04_config_fifo()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h136 struct drm_framebuffer base; member
156 struct drm_encoder base; member
207 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
593 struct drm_connector base; member
630 struct drm_connector_state base; member
636 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
651 struct drm_atomic_state base; member
775 u32 base; member
1436 struct drm_crtc base; member
1511 struct drm_plane base; member
1519 u32 base, cntl, size; global() member
1827 struct intel_encoder base; global() member
1872 struct intel_encoder base; global() member
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/third_party/icu/icu4j/main/classes/collate/src/com/ibm/icu/impl/coll/
H A DCollationDataBuilder.java52 base = null; in CollationDataBuilder()
73 base = b; in initForTailoring()
75 // For a tailoring, the default is to fall back to the base. in initForTailoring()
100 return base.isCompressibleLeadByte(b); in isCompressibleLeadByte()
186 // If c has contextual base mappings or if we add a contextual mapping, in addCE32()
187 // then copy the base mappings. in addCE32()
188 // Otherwise we just override the base mapping. in addCE32()
189 int baseCE32 = base.getFinalCE32(base.getCE32(c)); in addCE32()
277 ce32 = base in optimize()
1370 protected CollationData base; global() field in CollationDataBuilder
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/third_party/icu/ohos_icu4j/src/main/java/ohos/global/icu/impl/coll/
H A DCollationDataBuilder.java53 base = null; in CollationDataBuilder()
74 base = b; in initForTailoring()
76 // For a tailoring, the default is to fall back to the base. in initForTailoring()
101 return base.isCompressibleLeadByte(b); in isCompressibleLeadByte()
187 // If c has contextual base mappings or if we add a contextual mapping, in addCE32()
188 // then copy the base mappings. in addCE32()
189 // Otherwise we just override the base mapping. in addCE32()
190 int baseCE32 = base.getFinalCE32(base.getCE32(c)); in addCE32()
278 ce32 = base in optimize()
1339 protected CollationData base; global() field in CollationDataBuilder
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/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_resolve.c69 struct crocus_resource *rb_res = (void *) surf->base.texture; in disable_rb_aux_buffer()
72 surf->base.u.tex.level >= min_level && in disable_rb_aux_buffer()
73 surf->base.u.tex.level < min_level + num_levels) { in disable_rb_aux_buffer()
101 if (isv->res->base.b.target != PIPE_BUFFER) { in resolve_sampler_views()
117 (isv->base.format == PIPE_FORMAT_X24S8_UINT || in resolve_sampler_views()
118 isv->base.format == PIPE_FORMAT_X32_S8X24_UINT || in resolve_sampler_views()
119 isv->base.format == PIPE_FORMAT_S8_UINT)) { in resolve_sampler_views()
121 crocus_get_depth_stencil_resources(&batch->screen->devinfo, isv->base.texture, &zres, &sres); in resolve_sampler_views()
140 struct pipe_image_view *pview = &shs->image[i].base; in resolve_image_views()
143 if (res->base in resolve_image_views()
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/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-intel-mid.c276 u32 base, gpio, mask; in intel_mid_irq_handler() local
281 for (base = 0; base < priv->chip.ngpio; base += 32) { in intel_mid_irq_handler()
282 gedr = gpio_reg(&priv->chip, base, GEDR); in intel_mid_irq_handler()
289 base + gpio)); in intel_mid_irq_handler()
300 unsigned base; in intel_mid_irq_init_hw() local
302 for (base = 0; base < priv->chip.ngpio; base in intel_mid_irq_init_hw()
330 void __iomem *base; intel_gpio_probe() local
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H A Dgpio-merrifield.c341 unsigned long base, gpio; in mrfld_irq_handler() local
346 for (base = 0; base < priv->chip.ngpio; base += 32) { in mrfld_irq_handler()
347 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); in mrfld_irq_handler()
348 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); in mrfld_irq_handler()
360 irq = irq_find_mapping(gc->irq.domain, base + gpio); in mrfld_irq_handler()
372 unsigned int base; in mrfld_irq_init_hw() local
374 for (base = 0; base < pri in mrfld_irq_init_hw()
431 void __iomem *base; mrfld_gpio_probe() local
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/kernel/linux/linux-5.10/drivers/clk/socfpga/
H A Dclk-agilex.c329 void __iomem *base = data->base; in agilex_clk_register_c_perip() local
333 clk = s10_register_periph(&clks[i], base); in agilex_clk_register_c_perip()
348 void __iomem *base = data->base; in agilex_clk_register_cnt_perip() local
352 clk = s10_register_cnt_periph(&clks[i], base); in agilex_clk_register_cnt_perip()
367 void __iomem *base = data->base; in agilex_clk_register_gate() local
371 clk = s10_register_gate(&clks[i], base); in agilex_clk_register_gate()
387 void __iomem *base in agilex_clk_register_pll() local
411 void __iomem *base; __socfpga_agilex_clk_init() local
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H A Dclk-s10.c311 void __iomem *base = data->base; in s10_clk_register_c_perip() local
315 clk = s10_register_periph(&clks[i], base); in s10_clk_register_c_perip()
330 void __iomem *base = data->base; in s10_clk_register_cnt_perip() local
334 clk = s10_register_cnt_periph(&clks[i], base); in s10_clk_register_cnt_perip()
350 void __iomem *base = data->base; in s10_clk_register_gate() local
354 clk = s10_register_gate(&clks[i], base); in s10_clk_register_gate()
370 void __iomem *base in s10_clk_register_pll() local
394 void __iomem *base; __socfpga_s10_clk_init() local
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/kernel/linux/linux-5.10/drivers/ata/
H A Dsata_vsc.c38 /* Interrupt register offsets (from chip base address) */
57 /* DMA base */
62 /* SCRs base */
298 static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base) in vsc_sata_setup_port() argument
300 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; in vsc_sata_setup_port()
301 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; in vsc_sata_setup_port()
302 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; in vsc_sata_setup_port()
303 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; in vsc_sata_setup_port()
304 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; in vsc_sata_setup_port()
305 port->lbal_addr = base in vsc_sata_setup_port()
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/kernel/linux/linux-5.10/drivers/crypto/allwinner/sun4i-ss/
H A Dsun4i-ss-core.c48 .base = {
75 .base = {
97 .base = {
118 .base = {
140 .base = {
161 .base = {
183 .base = {
204 .base = {
222 .base = {
329 ss->base in sun4i_ss_probe()
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/kernel/linux/linux-5.10/drivers/mailbox/
H A Dmailbox-sti.c36 #define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4))
48 * @base: Base address of the register mapping region
56 void __iomem *base; member
126 void __iomem *base = MBOX_BASE(mdev, instance); in sti_mbox_enable_channel() local
130 writel_relaxed(BIT(channel), base + STI_ENA_SET_OFFSET); in sti_mbox_enable_channel()
141 void __iomem *base = MBOX_BASE(mdev, instance); in sti_mbox_disable_channel() local
145 writel_relaxed(BIT(channel), base + STI_ENA_CLR_OFFSET); in sti_mbox_disable_channel()
155 void __iomem *base = MBOX_BASE(mdev, instance); in sti_mbox_clear_irq() local
157 writel_relaxed(BIT(channel), base + STI_IRQ_CLR_OFFSET); in sti_mbox_clear_irq()
167 void __iomem *base in sti_mbox_irq_to_channel() local
257 void __iomem *base = MBOX_BASE(mdev, instance); sti_mbox_tx_is_ready() local
280 void __iomem *base = MBOX_BASE(mdev, instance); sti_mbox_send_data() local
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/kernel/linux/linux-5.10/drivers/phy/rockchip/
H A Dphy-rockchip-usb.c68 struct rockchip_usb_phy_base *base; member
85 return regmap_write(phy->base->reg_base, phy->reg_offset, val); in rockchip_usb_phy_power()
125 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val); in rockchip_usb_phy480m_is_enabled()
202 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base, in rockchip_usb_phy_init() argument
211 rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL); in rockchip_usb_phy_init()
215 rk_phy->base = base; in rockchip_usb_phy_init()
219 dev_err(base->dev, "missing reg property in node %pOFn\n", in rockchip_usb_phy_init()
236 while (base->pdata->phys[i].reg) { in rockchip_usb_phy_init()
237 if (base in rockchip_usb_phy_init()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
H A Dnouveau_usif.c36 struct drm_pending_event base; member
38 struct drm_event base; member
93 filp = ntfy->p->base.file_priv; in usif_notify()
111 if (!WARN_ON(filp->event_space < ntfy->p->e.base.length)) { in usif_notify()
112 list_add_tail(&ntfy->p->base.link, &filp->event_list); in usif_notify()
113 filp->event_space -= ntfy->p->e.base.length; in usif_notify()
125 struct nvif_client *client = &cli->base; in usif_notify_new()
170 struct nvif_client *client = &cli->base; in usif_notify_del()
193 struct nvif_client *client = &cli->base; in usif_notify_get()
212 ntfy->p->base in usif_notify_get()
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/kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/
H A Drockchip_drm_gem.c21 struct drm_device *drm = rk_obj->base.dev; in rockchip_gem_iommu_map()
28 rk_obj->base.size, PAGE_SIZE, in rockchip_gem_iommu_map()
41 if (ret < (ssize_t)rk_obj->base.size) { in rockchip_gem_iommu_map()
43 ret, rk_obj->base.size); in rockchip_gem_iommu_map()
62 struct drm_device *drm = rk_obj->base.dev; in rockchip_gem_iommu_unmap()
78 struct drm_device *drm = rk_obj->base.dev; in rockchip_gem_get_pages()
82 rk_obj->pages = drm_gem_get_pages(&rk_obj->base); in rockchip_gem_get_pages()
86 rk_obj->num_pages = rk_obj->base.size >> PAGE_SHIFT; in rockchip_gem_get_pages()
88 rk_obj->sgt = drm_prime_pages_to_sg(rk_obj->base.dev, in rockchip_gem_get_pages()
110 drm_gem_put_pages(&rk_obj->base, rk_ob in rockchip_gem_get_pages()
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/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-88pm860x.c82 unsigned long ticks, base, data; in pm860x_rtc_read_time() local
87 base = ((unsigned long)buf[1] << 24) | (buf[3] << 16) | in pm860x_rtc_read_time()
94 ticks = base + data; in pm860x_rtc_read_time()
95 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm860x_rtc_read_time()
96 base, data, ticks); in pm860x_rtc_read_time()
107 unsigned long ticks, base, data; in pm860x_rtc_set_time() local
115 base = ticks - data; in pm860x_rtc_set_time()
116 dev_dbg(info->dev, "set base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm860x_rtc_set_time()
117 base, data, ticks); in pm860x_rtc_set_time()
119 pm860x_page_reg_write(info->i2c, REG0_DATA, (base >> 2 in pm860x_rtc_set_time()
131 unsigned long ticks, base, data; pm860x_rtc_read_alarm() local
157 unsigned long ticks, base, data; pm860x_rtc_set_alarm() local
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/kernel/linux/linux-5.10/drivers/spi/
H A Dspi-sprd-adi.c113 void __iomem *base; member
144 sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS); in sprd_adi_drain_fifo()
161 return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL; in sprd_adi_fifo_is_full()
185 writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD); in sprd_adi_read()
194 val = readl_relaxed(sadi->base + REG_ADI_RD_DATA); in sprd_adi_read()
418 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL); in sprd_adi_hw_init()
419 writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH); in sprd_adi_hw_init()
422 tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0); in sprd_adi_hw_init()
424 writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0); in sprd_adi_hw_init()
443 writel_relaxed(chn_config, sadi->base in sprd_adi_hw_init()
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/kernel/linux/linux-6.6/drivers/ata/
H A Dsata_vsc.c38 /* Interrupt register offsets (from chip base address) */
57 /* DMA base */
62 /* SCRs base */
298 static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base) in vsc_sata_setup_port() argument
300 port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET; in vsc_sata_setup_port()
301 port->data_addr = base + VSC_SATA_TF_DATA_OFFSET; in vsc_sata_setup_port()
302 port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET; in vsc_sata_setup_port()
303 port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET; in vsc_sata_setup_port()
304 port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET; in vsc_sata_setup_port()
305 port->lbal_addr = base in vsc_sata_setup_port()
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/kernel/linux/linux-6.6/drivers/watchdog/
H A Dstarfive-wdt.c103 void __iomem *base; member
208 writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
214 writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
223 val = readl(wdt->base + wdt->variant->control); in starfive_wdt_enable_reset()
225 writel(val, wdt->base + wdt->variant->control); in starfive_wdt_enable_reset()
231 return !!readl(wdt->base + wdt->variant->int_status); in starfive_wdt_raise_irq_status()
239 return readl_poll_timeout_atomic(wdt->base + wdt->variant->int_clr, value, in starfive_wdt_wait_int_free()
255 writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr); in starfive_wdt_int_clr()
262 writel(val, wdt->base + wdt->variant->load); in starfive_wdt_set_count()
267 return readl(wdt->base in starfive_wdt_get_count()
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/kernel/linux/linux-6.6/include/linux/
H A Dcoresight.h119 * @base : When io_mem == true, base address of the component
126 void __iomem *base; member
138 .base = (_addr), \
386 return readl_relaxed(csa->base + offset); in csdev_access_relaxed_read32()
393 static inline u32 coresight_get_cid(void __iomem *base) in coresight_get_cid() argument
398 cid |= readl(base + CORESIGHT_CIDRn(i)) << (i * 8); in coresight_get_cid()
403 static inline bool is_coresight_device(void __iomem *base) in is_coresight_device() argument
405 u32 cid = coresight_get_cid(base); in is_coresight_device()
452 return readl_relaxed(csa->base in csdev_access_relaxed_read_pair()
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/kernel/linux/linux-6.6/drivers/rtc/
H A Drtc-88pm860x.c82 unsigned long ticks, base, data; in pm860x_rtc_read_time() local
87 base = ((unsigned long)buf[1] << 24) | (buf[3] << 16) | in pm860x_rtc_read_time()
94 ticks = base + data; in pm860x_rtc_read_time()
95 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm860x_rtc_read_time()
96 base, data, ticks); in pm860x_rtc_read_time()
107 unsigned long ticks, base, data; in pm860x_rtc_set_time() local
115 base = ticks - data; in pm860x_rtc_set_time()
116 dev_dbg(info->dev, "set base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm860x_rtc_set_time()
117 base, data, ticks); in pm860x_rtc_set_time()
119 pm860x_page_reg_write(info->i2c, REG0_DATA, (base >> 2 in pm860x_rtc_set_time()
131 unsigned long ticks, base, data; pm860x_rtc_read_alarm() local
157 unsigned long ticks, base, data; pm860x_rtc_set_alarm() local
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/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-imx-tpm.c62 void __iomem *base; member
148 val = readl(tpm->base + PWM_IMX_TPM_SC); in pwm_imx_tpm_get_state()
150 tmp = readl(tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); in pwm_imx_tpm_get_state()
155 val = readl(tpm->base + PWM_IMX_TPM_CnSC(pwm->hwpwm)); in pwm_imx_tpm_get_state()
194 val = readl(tpm->base + PWM_IMX_TPM_SC); in pwm_imx_tpm_apply_hw()
203 writel(val, tpm->base + PWM_IMX_TPM_SC); in pwm_imx_tpm_apply_hw()
213 writel(p->mod, tpm->base + PWM_IMX_TPM_MOD); in pwm_imx_tpm_apply_hw()
233 writel(p->val, tpm->base + PWM_IMX_TPM_CnV(pwm->hwpwm)); in pwm_imx_tpm_apply_hw()
241 while (readl(tpm->base + PWM_IMX_TPM_MOD) != p->mod in pwm_imx_tpm_apply_hw()
242 || readl(tpm->base in pwm_imx_tpm_apply_hw()
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/kernel/linux/linux-6.6/drivers/clk/microchip/
H A Dclk-mpfs.c35 void __iomem *base; member
41 void __iomem *base; member
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_round_rate()
136 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_set_rate()
137 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_set_rate()
138 void __iomem *postdiv_addr = msspll_hw->base in mpfs_clk_msspll_set_rate()
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/kernel/linux/linux-6.6/drivers/clk/socfpga/
H A Dclk-s10.c310 void __iomem *base = data->base; in s10_clk_register_c_perip() local
314 hw_clk = s10_register_periph(&clks[i], base); in s10_clk_register_c_perip()
329 void __iomem *base = data->base; in s10_clk_register_cnt_perip() local
333 hw_clk = s10_register_cnt_periph(&clks[i], base); in s10_clk_register_cnt_perip()
349 void __iomem *base = data->base; in s10_clk_register_gate() local
353 hw_clk = s10_register_gate(&clks[i], base); in s10_clk_register_gate()
369 void __iomem *base in s10_clk_register_pll() local
390 void __iomem *base; s10_clkmgr_init() local
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