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/third_party/node/deps/zlib/google/
H A Dzip_unittest.cc15 #include "base/files/file.h"
16 #include "base/files/file_enumerator.h"
17 #include "base/files/file_path.h"
18 #include "base/files/file_util.h"
19 #include "base/files/scoped_temp_dir.h"
20 #include "base/functional/bind.h"
21 #include "base/logging.h"
22 #include "base/path_service.h"
23 #include "base/strings/strcat.h"
24 #include "base/string
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/third_party/skia/third_party/externals/zlib/google/
H A Dzip_unittest.cc13 #include "base/bind.h"
14 #include "base/files/file.h"
15 #include "base/files/file_enumerator.h"
16 #include "base/files/file_path.h"
17 #include "base/files/file_util.h"
18 #include "base/files/scoped_temp_dir.h"
19 #include "base/logging.h"
20 #include "base/macros.h"
21 #include "base/path_service.h"
22 #include "base/string
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H A Dzip.h10 #include "base/callback.h"
11 #include "base/files/file_path.h"
12 #include "base/files/platform_file.h"
13 #include "base/time/time.h"
16 namespace base { namespace
34 DirectoryContentEntry(const base::FilePath& path, bool is_directory) in DirectoryContentEntry()
36 base::FilePath path;
42 virtual std::vector<base::File> OpenFilesForReading(
43 const std::vector<base::FilePath>& paths) = 0;
45 virtual bool DirectoryExists(const base
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/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx6sx.c123 void __iomem *base; in imx6sx_clocks_init() local
147 base = of_iomap(np, 0); in imx6sx_clocks_init()
148 WARN_ON(!base); in imx6sx_clocks_init()
151 hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
152 hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
153 hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
154 hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
155 hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
156 hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
157 hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base in imx6sx_clocks_init()
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H A Dclk-imx8mn.c291 void __iomem *base; in imx8mn_clocks_probe() local
311 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
313 if (WARN_ON(IS_ERR(base))) { in imx8mn_clocks_probe()
314 ret = PTR_ERR(base); in imx8mn_clocks_probe()
318 hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
319 hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
320 hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
321 hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
322 hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
323 hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base in imx8mn_clocks_probe()
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H A Dclk-imx6sl.c184 void __iomem *base; in imx6sl_clocks_init() local
202 base = of_iomap(np, 0); in imx6sl_clocks_init()
203 WARN_ON(!base); in imx6sl_clocks_init()
205 anatop_base = base; in imx6sl_clocks_init()
207 hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
208 hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
209 hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
210 hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
211 hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
212 hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base in imx6sl_clocks_init()
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/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx6sx.c123 void __iomem *base; in imx6sx_clocks_init() local
147 base = of_iomap(np, 0); in imx6sx_clocks_init()
148 WARN_ON(!base); in imx6sx_clocks_init()
151 hws[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
152 hws[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
153 hws[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
154 hws[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
155 hws[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
156 hws[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sx_clocks_init()
157 hws[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base in imx6sx_clocks_init()
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H A Dclk-imx8ulp.c53 void __iomem *base; member
91 val = readl(pcc_reset->base + offset); in imx8ulp_pcc_assert()
93 writel(val, pcc_reset->base + offset); in imx8ulp_pcc_assert()
109 val = readl(pcc_reset->base + offset); in imx8ulp_pcc_deassert()
111 writel(val, pcc_reset->base + offset); in imx8ulp_pcc_deassert()
123 static int imx8ulp_pcc_reset_init(struct platform_device *pdev, void __iomem *base, in imx8ulp_pcc_reset_init() argument
134 pcc_reset->base = base; in imx8ulp_pcc_reset_init()
150 void __iomem *base; in imx8ulp_clk_cgc1_init() local
163 base in imx8ulp_clk_cgc1_init()
234 void __iomem *base; imx8ulp_clk_cgc2_init() local
316 void __iomem *base; imx8ulp_clk_pcc3_init() local
399 void __iomem *base; imx8ulp_clk_pcc4_init() local
454 void __iomem *base; imx8ulp_clk_pcc5_init() local
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H A Dclk-imx8mn.c323 void __iomem *base; in imx8mn_clocks_probe() local
343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
345 if (WARN_ON(IS_ERR(base))) { in imx8mn_clocks_probe()
346 ret = PTR_ERR(base); in imx8mn_clocks_probe()
350 hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
351 hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
352 hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
353 hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
354 hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); in imx8mn_clocks_probe()
355 hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base in imx8mn_clocks_probe()
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H A Dclk-imx6ul.c131 void __iomem *base; in imx6ul_clocks_init() local
151 base = of_iomap(np, 0); in imx6ul_clocks_init()
153 WARN_ON(!base); in imx6ul_clocks_init()
155 hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
156 hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
157 hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
158 hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
159 hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
160 hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6ul_clocks_init()
161 hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base in imx6ul_clocks_init()
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H A Dclk-imx6sl.c185 void __iomem *base; in imx6sl_clocks_init() local
203 base = of_iomap(np, 0); in imx6sl_clocks_init()
204 WARN_ON(!base); in imx6sl_clocks_init()
206 anatop_base = base; in imx6sl_clocks_init()
208 hws[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
209 hws[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
210 hws[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
211 hws[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
212 hws[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); in imx6sl_clocks_init()
213 hws[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base in imx6sl_clocks_init()
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_28nm_8960.c14 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
16 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
20 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_3, 0x0); in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_8960_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base in dsi_28nm_dphy_set_timing()
44 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_init() local
56 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_ctrl() local
67 void __iomem *base = phy->reg_base; dsi_28nm_phy_calibration() local
97 void __iomem *base = phy->base; dsi_28nm_phy_lane_config() local
124 void __iomem *base = phy->base; dsi_28nm_phy_enable() local
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H A Ddsi_phy_28nm.c12 void __iomem *base = phy->base; in dsi_28nm_dphy_set_timing() local
14 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0, in dsi_28nm_dphy_set_timing()
16 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1, in dsi_28nm_dphy_set_timing()
18 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2, in dsi_28nm_dphy_set_timing()
21 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3, in dsi_28nm_dphy_set_timing()
23 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4, in dsi_28nm_dphy_set_timing()
25 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5, in dsi_28nm_dphy_set_timing()
27 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6, in dsi_28nm_dphy_set_timing()
29 dsi_phy_write(base in dsi_28nm_dphy_set_timing()
44 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_enable_dcdc() local
59 void __iomem *base = phy->reg_base; dsi_28nm_phy_regulator_enable_ldo() local
94 void __iomem *base = phy->base; dsi_28nm_phy_enable() local
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/kernel/linux/linux-5.10/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base)
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/kernel/linux/linux-6.6/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dtopaz_pcie_regs.h8 #define PCIE_DMA_WR_INTR_STATUS(base) ((base) + 0x9bc)
9 #define PCIE_DMA_WR_INTR_MASK(base) ((base) + 0x9c4)
10 #define PCIE_DMA_WR_INTR_CLR(base) ((base) + 0x9c8)
11 #define PCIE_DMA_WR_ERR_STATUS(base) ((base) + 0x9cc)
12 #define PCIE_DMA_WR_DONE_IMWR_ADDR_LOW(base) ((base)
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/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_fw_defs.h15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
33 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
35 (IRO[324].base
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/kernel/linux/linux-6.6/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_fw_defs.h15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
17 (IRO[151].base + ((assertListEntry) * IRO[151].m1))
19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
33 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
35 (IRO[324].base
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/kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_scaler.h30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0)
31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10)
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20)
33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24)
34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base)
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/kernel/linux/linux-6.6/drivers/gpu/drm/sun4i/
H A Dsun8i_vi_scaler.h30 #define SUN8I_SCALER_VSU_CTRL(base) ((base) + 0x0)
31 #define SUN50I_SCALER_VSU_SCALE_MODE(base) ((base) + 0x10)
32 #define SUN50I_SCALER_VSU_DIR_THR(base) ((base) + 0x20)
33 #define SUN50I_SCALER_VSU_EDGE_THR(base) ((base) + 0x24)
34 #define SUN50I_SCALER_VSU_EDSCL_CTRL(base) ((base)
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/kernel/linux/linux-5.10/drivers/scsi/
H A Daha1740.h19 #define HID0(base) (base + 0x0)
20 #define HID1(base) (base + 0x1)
21 #define HID2(base) (base + 0x2)
22 #define HID3(base) (base + 0x3)
23 #define EBCNTRL(base) (base
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/kernel/linux/linux-6.6/drivers/scsi/
H A Daha1740.h19 #define HID0(base) (base + 0x0)
20 #define HID1(base) (base + 0x1)
21 #define HID2(base) (base + 0x2)
22 #define HID3(base) (base + 0x3)
23 #define EBCNTRL(base) (base
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/kernel/linux/linux-5.10/arch/mips/alchemy/common/
H A Dusb.c6 * area. Au1550 has OHCI on different base address. No need to handle
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
123 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) in __au1300_ohci_control() argument
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
134 __raw_writel(r, base in __au1300_ohci_control()
163 __au1300_ehci_control(void __iomem *base, int enable) __au1300_ehci_control() argument
204 __au1300_udc_control(void __iomem *base, int enable) __au1300_udc_control() argument
235 __au1300_otg_control(void __iomem *base, int enable) __au1300_otg_control() argument
267 void __iomem *base = au1300_usb_control() local
295 void __iomem *base = au1300_usb_init() local
316 __au1200_ohci_control(void __iomem *base, int enable) __au1200_ohci_control() argument
330 __au1200_ehci_control(void __iomem *base, int enable) __au1200_ehci_control() argument
346 __au1200_udc_control(void __iomem *base, int enable) __au1200_udc_control() argument
362 void __iomem *base = au1200_usb_control() local
385 void __iomem *base = au1200_usb_init() local
394 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); au1000_usb_init() local
427 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); __au1xx0_ohci_control() local
514 void __iomem *base = (void __iomem *)KSEG1ADDR(br); au1000_usb_pm() local
531 void __iomem *base = au1200_usb_pm() local
551 void __iomem *base = au1300_usb_pm() local
[all...]
/kernel/linux/linux-6.6/arch/mips/alchemy/common/
H A Dusb.c6 * area. Au1550 has OHCI on different base address. No need to handle
98 static inline void __au1300_usb_phyctl(void __iomem *base, int enable) in __au1300_usb_phyctl() argument
102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
123 static inline void __au1300_ohci_control(void __iomem *base, int enable, int id) in __au1300_ohci_control() argument
128 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
131 r = __raw_readl(base + USB_DWC_CTRL3); /* enable OHCI block */ in __au1300_ohci_control()
134 __raw_writel(r, base in __au1300_ohci_control()
163 __au1300_ehci_control(void __iomem *base, int enable) __au1300_ehci_control() argument
204 __au1300_udc_control(void __iomem *base, int enable) __au1300_udc_control() argument
235 __au1300_otg_control(void __iomem *base, int enable) __au1300_otg_control() argument
267 void __iomem *base = au1300_usb_control() local
295 void __iomem *base = au1300_usb_init() local
316 __au1200_ohci_control(void __iomem *base, int enable) __au1200_ohci_control() argument
330 __au1200_ehci_control(void __iomem *base, int enable) __au1200_ehci_control() argument
346 __au1200_udc_control(void __iomem *base, int enable) __au1200_udc_control() argument
362 void __iomem *base = au1200_usb_control() local
385 void __iomem *base = au1200_usb_init() local
394 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); au1000_usb_init() local
427 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); __au1xx0_ohci_control() local
514 void __iomem *base = (void __iomem *)KSEG1ADDR(br); au1000_usb_pm() local
531 void __iomem *base = au1200_usb_pm() local
551 void __iomem *base = au1300_usb_pm() local
[all...]
/third_party/typescript/tests/baselines/reference/
H A DdeclarationEmitNameConflicts2.js2 module X.Y.base {
11 module X.Y.base.Z {
12 export var f = X.Y.base.f; // Should be base.f
13 export var C = X.Y.base.C; // Should be base.C
14 export var M = X.Y.base.M; // Should be base.M
15 export var E = X.Y.base.E; // Should be base
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_20nm.c13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing() local
15 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0, in dsi_20nm_dphy_set_timing()
17 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1, in dsi_20nm_dphy_set_timing()
19 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2, in dsi_20nm_dphy_set_timing()
22 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3, in dsi_20nm_dphy_set_timing()
24 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4, in dsi_20nm_dphy_set_timing()
26 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5, in dsi_20nm_dphy_set_timing()
28 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6, in dsi_20nm_dphy_set_timing()
30 dsi_phy_write(base in dsi_20nm_dphy_set_timing()
45 void __iomem *base = phy->reg_base; dsi_20nm_phy_regulator_ctrl() local
72 void __iomem *base = phy->base; dsi_20nm_phy_enable() local
[all...]

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