/kernel/linux/linux-5.10/drivers/watchdog/ |
H A D | f71808e_wdt.c | 130 static inline int superio_inb(int base, int reg); 131 static inline int superio_inw(int base, int reg); 132 static inline void superio_outb(int base, int reg, u8 val); 133 static inline void superio_set_bit(int base, int reg, int bit); 134 static inline void superio_clear_bit(int base, int reg, int bit); 135 static inline int superio_enter(int base); 136 static inline void superio_select(int base, int ld); 137 static inline void superio_exit(int base); 160 static inline int superio_inb(int base, int reg) in superio_inb() argument 162 outb(reg, base); in superio_inb() 166 superio_inw(int base, int reg) superio_inw() argument 174 superio_outb(int base, int reg, u8 val) superio_outb() argument 180 superio_set_bit(int base, int reg, int bit) superio_set_bit() argument 187 superio_clear_bit(int base, int reg, int bit) superio_clear_bit() argument 194 superio_enter(int base) superio_enter() argument 209 superio_select(int base, int ld) superio_select() argument 215 superio_exit(int base) superio_exit() argument [all...] |
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
H A D | intel_dp_hdcp.c | 35 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_write_an_aksv() 70 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_read_bksv() 86 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_read_bstatus() 108 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_read_bcaps() 141 struct drm_i915_private *i915 = to_i915(dig_port->base.base in intel_dp_hdcp_read_ri_prime() [all...] |
H A D | intel_hotplug.c | 188 if (connector->base.polled != DRM_CONNECTOR_POLL_HPD) in intel_hpd_irq_storm_switch_to_polling() 199 connector->base.name); in intel_hpd_irq_storm_switch_to_polling() 202 connector->base.polled = DRM_CONNECTOR_POLL_CONNECT | in intel_hpd_irq_storm_switch_to_polling() 238 if (connector->base.polled != connector->polled) in intel_hpd_irq_storm_reenable_work() 241 connector->base.name); in intel_hpd_irq_storm_reenable_work() 242 connector->base.polled = connector->polled; in intel_hpd_irq_storm_reenable_work() 263 struct drm_device *dev = connector->base.dev; in intel_encoder_hotplug() 269 old_status = connector->base.status; in intel_encoder_hotplug() 270 old_epoch_counter = connector->base.epoch_counter; in intel_encoder_hotplug() 272 connector->base in intel_encoder_hotplug() [all...] |
/kernel/linux/linux-6.6/drivers/fsi/ |
H A D | fsi-master-aspeed.c | 25 void __iomem *base; member 100 void __iomem *base = aspeed->base; in __opb_write() local 108 writel_relaxed(CMD_WRITE, base + OPB0_RW); in __opb_write() 109 writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); in __opb_write() 110 writel_relaxed(addr, base + OPB0_FSI_ADDR); in __opb_write() 111 writel_relaxed(val, base + OPB0_FSI_DATA_W); in __opb_write() 112 writel_relaxed(0x1, base + OPB_IRQ_CLEAR); in __opb_write() 113 writel(0x1, base + OPB_TRIGGER); in __opb_write() 115 ret = readl_poll_timeout(base in __opb_write() 152 void __iomem *base = aspeed->base; __opb_read() local [all...] |
/kernel/linux/linux-6.6/drivers/iio/adc/ |
H A D | mxs-lradc-adc.c | 117 void __iomem *base; member 157 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single() 158 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single() 163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single() 166 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single() 170 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single() 171 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single() 173 writel(0, adc->base + LRADC_CH(0)); in mxs_lradc_adc_read_single() 177 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single() 178 writel(BIT(0), adc->base in mxs_lradc_adc_read_single() [all...] |
/third_party/node/deps/v8/src/wasm/ |
H A D | streaming-decoder.cc | 7 #include "src/base/platform/wrappers.h" 36 void OnBytesReceived(base::Vector<const uint8_t> bytes) override; 59 base::Vector<const uint8_t> length_bytes) in SectionBuffer() 62 bytes_(base::OwnedVector<uint8_t>::NewForOverwrite( in SectionBuffer() 73 base::Vector<const uint8_t> GetCode(WireBytesRef ref) const final { 80 base::Optional<ModuleWireBytes> GetModuleBytes() const final { return {}; } 83 base::Vector<uint8_t> bytes() const { return bytes_.as_vector(); } in bytes() 84 base::Vector<uint8_t> payload() const { return bytes() + payload_offset_; } in payload() 90 const base::OwnedVector<uint8_t> bytes_; 127 base [all...] |
/third_party/mesa3d/src/virtio/vulkan/ |
H A D | vn_image.c | 231 vn_object_base_init(&img->base, VK_OBJECT_TYPE_IMAGE, &dev->base); in vn_image_create() 235 vn_object_base_fini(&img->base); in vn_image_create() 269 vn_object_base_init(&img->base, VK_OBJECT_TYPE_IMAGE, &dev->base); in vn_image_create_deferred() 273 vn_object_base_fini(&img->base); in vn_image_create_deferred() 294 pAllocator ? pAllocator : &dev->base.base.alloc; in vn_CreateImage() 350 pAllocator ? pAllocator : &dev->base.base in vn_DestroyImage() [all...] |
/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/ |
H A D | nv30_screen.c | 525 struct nouveau_pushbuf *push = screen->base.pushbuf; in nv30_screen_fence_emit() 527 *sequence = ++screen->base.fence.sequence; in nv30_screen_fence_emit() 549 if (!nouveau_drm_screen_unref(&screen->base)) in nv30_screen_destroy() 552 nouveau_fence_cleanup(&screen->base); in nv30_screen_destroy() 571 nouveau_screen_fini(&screen->base); in nv30_screen_destroy() 578 screen->base.base.context_create = NULL; \ 579 return &screen->base; \ 627 pscreen = &screen->base.base; in nv30_screen_create() [all...] |
/third_party/node/deps/v8/src/heap/ |
H A D | memory-allocator.cc | 9 #include "src/base/address-region.h" 189 base::MutexGuard guard(&mutex_); in NumberOfCommittedChunks() 195 base::MutexGuard guard(&mutex_); in NumberOfChunks() 204 base::MutexGuard guard(&mutex_); in CommittedBufferedMemory() 219 Address base = reservation->address(); in CommitMemory() local 221 if (!reservation->SetPermissions(base, size, PageAllocator::kReadWrite)) { in CommitMemory() 224 UpdateAllocatedSpaceLimits(base, base + size); in CommitMemory() 238 Address base, size_t size) { in FreeMemoryRegion() 239 FreePages(page_allocator, reinterpret_cast<void*>(base), siz in FreeMemoryRegion() 237 FreeMemoryRegion(v8::PageAllocator* page_allocator, Address base, size_t size) FreeMemoryRegion() argument 264 Address base = reservation.address(); AllocateAlignedMemory() local 357 Address base = AllocateUninitializedChunk() local [all...] |
/kernel/linux/linux-6.6/drivers/net/can/ |
H A D | sun4i_can.c | 67 /* Registers address (physical base address 0x01C2BC00) */ 218 void __iomem *base; member 242 writel(val, priv->base + SUN4I_REG_CMD_ADDR); in sun4i_can_write_cmdreg() 253 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); in set_normal_mode() 255 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); in set_normal_mode() 258 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) { in set_normal_mode() 274 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); in set_reset_mode() 276 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); in set_reset_mode() 279 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) & in set_reset_mode() 303 writel(cfg, priv->base in sun4ican_set_bittiming() [all...] |
/kernel/linux/linux-6.6/drivers/thermal/mediatek/ |
H A D | lvts_thermal.c | 120 void __iomem *base; member 133 void __iomem *base; member 143 void __iomem *base; member 223 regset->base = lvts_ctrl->base; in lvts_debugfs_init() 320 value = readl(LVTS_MONINT(lvts_ctrl->base)); in lvts_update_irq_mask() 330 writel(value, LVTS_MONINT(lvts_ctrl->base)); in lvts_update_irq_mask() 352 void __iomem *base = lvts_sensor->base; in lvts_set_trips() local 381 writel(raw_low, LVTS_OFFSETL(base)); in lvts_set_trips() [all...] |
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 56 container_of(clk_mgr, struct clk_mgr_vgh, base) 157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks() 158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks() 563 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in vg_clk_mgr_helper_populate_bw_params() 667 clk_mgr->base.base.ctx = ctx; in vg_clk_mgr_construct() 668 clk_mgr->base.base.funcs = &vg_funcs; in vg_clk_mgr_construct() 670 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct() 672 clk_mgr->base in vg_clk_mgr_construct() [all...] |
/third_party/mesa3d/src/gallium/drivers/r300/ |
H A D | r300_texture.c | 991 struct r300_resource *tex = r300_resource(surf->base.texture); in r300_texture_setup_fb_state() 992 unsigned level = surf->base.u.tex.level; in r300_texture_setup_fb_state() 994 r300_stride_to_width(surf->base.format, tex->tex.stride_in_bytes[level]); in r300_texture_setup_fb_state() 997 if (util_format_is_depth_or_stencil(surf->base.format)) { in r300_texture_setup_fb_state() 1002 R300_DEPTHENDIAN(r300_get_endian_swap(surf->base.format)); in r300_texture_setup_fb_state() 1003 surf->format = r300_translate_zsformat(surf->base.format); in r300_texture_setup_fb_state() 1007 enum pipe_format format = util_format_linear(surf->base.format); in r300_texture_setup_fb_state() 1044 const struct pipe_resource *base, in r300_texture_create_object() 1061 tex->b.usage = base->usage; in r300_texture_create_object() 1062 tex->b.bind = base in r300_texture_create_object() 1043 r300_texture_create_object(struct r300_screen *rscreen, const struct pipe_resource *base, enum radeon_bo_layout microtile, enum radeon_bo_layout macrotile, unsigned stride_in_bytes_override, struct pb_buffer *buffer) r300_texture_create_object() argument 1129 r300_texture_create(struct pipe_screen *screen, const struct pipe_resource *base) r300_texture_create() argument 1150 r300_texture_from_handle(struct pipe_screen *screen, const struct pipe_resource *base, struct winsys_handle *whandle, unsigned usage) r300_texture_from_handle() argument [all...] |
/third_party/skia/third_party/externals/abseil-cpp/absl/strings/ |
H A D | numbers.cc | 33 #include "absl/base/attributes.h" 34 #include "absl/base/internal/raw_logging.h" 361 // into a base-10 exponent and 6 ASCII digits, where the first digit is never 372 // in the output ASCII array, and exp is the base-10 exponent. It would be in SplitToSix() 373 // faster to use a table here, and to look up the base-2 exponent of value, in SplitToSix() 434 // track the base-2 exponent of both sides. This greatly simplifies the in SplitToSix() 642 int base = *base_ptr; in safe_parse_sign_and_base() local 664 // Consume base-dependent prefix. in safe_parse_sign_and_base() 665 // base 0: "0x" -> base 1 in safe_parse_sign_and_base() 917 safe_parse_positive_int(absl::string_view text, int base, IntType* value_p) safe_parse_positive_int() argument 953 safe_parse_negative_int(absl::string_view text, int base, IntType* value_p) safe_parse_negative_int() argument [all...] |
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_resource.c | 892 return &dpp->base; in dcn30_dpp_create() 912 return &opp->base; in dcn30_opp_create() 932 return &aux_engine->base; in dcn30_aux_engine_create() 988 return &mpc30->base; in dcn30_mpc_create() 1017 return &hubbub3->base; in dcn30_hubbub_create() 1030 tgn10->base.inst = instance; in dcn30_timing_generator_create() 1031 tgn10->base.ctx = ctx; in dcn30_timing_generator_create() 1039 return &tgn10->base; in dcn30_timing_generator_create() 1072 return &enc20->enc10.base; in dcn30_link_encoder_create() 1089 return &panel_cntl->base; in dcn30_panel_cntl_create() [all...] |
/third_party/mesa3d/src/gallium/drivers/d3d12/ |
H A D | d3d12_context.cpp | 510 cso->base = *rs_state; in d3d12_create_rasterizer_state() 517 cso->base.cull_face = PIPE_FACE_BACK; in d3d12_create_rasterizer_state() 809 struct pipe_sampler_view *state = &sampler_view->base; in d3d12_init_sampler_view_descriptor() 837 assert(offset == 0 || res->base.b.target == PIPE_BUFFER); in d3d12_init_sampler_view_descriptor() 932 sampler_view->base = *state; in d3d12_create_sampler_view() 933 sampler_view->base.texture = NULL; in d3d12_create_sampler_view() 934 pipe_resource_reference(&sampler_view->base.texture, texture); in d3d12_create_sampler_view() 935 sampler_view->base.reference.count = 1; in d3d12_create_sampler_view() 936 sampler_view->base.context = pctx; in d3d12_create_sampler_view() 943 format_info.swizzle[sampler_view->base in d3d12_create_sampler_view() [all...] |
/third_party/mesa3d/src/gallium/drivers/v3d/ |
H A D | v3d_program.c | 106 v3d_get_slot_for_driver_location(so->base.ir.nir, output->register_index); in v3d_set_transform_feedback_outputs() 162 so->base.stream_output.stride[buffer] = in v3d_set_transform_feedback_outputs() 167 so->tf_outputs = ralloc_array(so->base.ir.nir, struct v3d_varying_slot, in v3d_set_transform_feedback_outputs() 208 nir_shader *s = so->base.ir.nir; in v3d_shader_precompile() 212 .base.shader_state = so, in v3d_shader_precompile() 226 v3d_setup_shared_precompile_key(so, &key.base); in v3d_shader_precompile() 227 v3d_get_compiled_shader(v3d, &key.base, sizeof(key)); in v3d_shader_precompile() 230 .base.shader_state = so, in v3d_shader_precompile() 231 .base.is_last_geometry_stage = true, in v3d_shader_precompile() 234 v3d_setup_shared_precompile_key(so, &key.base); in v3d_shader_precompile() [all...] |
/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/ |
H A D | nv84_video.c | 136 assert(target->base.buffer_format == PIPE_FORMAT_NV12); in nv84_decoder_decode_bitstream_h264() 193 align(0x20 * mb(dec->base.width) * mb(dec->base.height), 0x100); in nv84_decoder_begin_frame_mpeg12() 268 struct nouveau_screen *screen = &nv50->screen->base; in nv84_create_decoder() 297 dec->base = *templ; in nv84_create_decoder() 298 dec->base.context = context; in nv84_create_decoder() 299 dec->base.destroy = nv84_decoder_destroy; in nv84_create_decoder() 300 dec->base.flush = nv84_decoder_flush; in nv84_create_decoder() 302 dec->base.decode_bitstream = nv84_decoder_decode_bitstream_h264; in nv84_create_decoder() 303 dec->base in nv84_create_decoder() [all...] |
/kernel/linux/linux-5.10/drivers/gpio/ |
H A D | gpio-mxs.c | 48 void __iomem *base; member 87 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; in mxs_gpio_set_irq_type() 111 pin_addr = port->base + PINCTRL_IRQLEV(port); in mxs_gpio_set_irq_type() 114 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); in mxs_gpio_set_irq_type() 117 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); in mxs_gpio_set_irq_type() 121 pin_addr = port->base + PINCTRL_IRQPOL(port); in mxs_gpio_set_irq_type() 127 writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); in mxs_gpio_set_irq_type() 139 pin_addr = port->base + PINCTRL_IRQPOL(port); in mxs_flip_edge() 157 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) & in mxs_gpio_irq_handler() 158 readl(port->base in mxs_gpio_irq_handler() 281 static void __iomem *base; mxs_gpio_probe() local [all...] |
/kernel/linux/linux-5.10/drivers/i2c/busses/ |
H A D | i2c-altera.c | 59 * @base: pointer to register struct 75 void __iomem *base; member 96 int_en = readl(idev->base + ALTR_I2C_ISER); in altr_i2c_int_enable() 102 writel(idev->isr_mask, idev->base + ALTR_I2C_ISER); in altr_i2c_int_enable() 107 u32 int_en = readl(idev->base + ALTR_I2C_ISR); in altr_i2c_int_clear() 109 writel(int_en | mask, idev->base + ALTR_I2C_ISR); in altr_i2c_int_clear() 114 u32 tmp = readl(idev->base + ALTR_I2C_CTRL); in altr_i2c_core_disable() 116 writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); in altr_i2c_core_disable() 121 u32 tmp = readl(idev->base + ALTR_I2C_CTRL); in altr_i2c_core_enable() 123 writel(tmp | ALTR_I2C_CTRL_EN, idev->base in altr_i2c_core_enable() [all...] |
/kernel/linux/linux-5.10/drivers/tty/ |
H A D | goldfish.c | 39 void __iomem *base; member 59 void __iomem *base = qtty->base; in do_rw_io() local 62 gf_write_ptr((void *)address, base + GOLDFISH_TTY_REG_DATA_PTR, in do_rw_io() 63 base + GOLDFISH_TTY_REG_DATA_PTR_HIGH); in do_rw_io() 64 writel(count, base + GOLDFISH_TTY_REG_DATA_LEN); in do_rw_io() 68 base + GOLDFISH_TTY_REG_CMD); in do_rw_io() 71 base + GOLDFISH_TTY_REG_CMD); in do_rw_io() 140 void __iomem *base = qtty->base; in goldfish_tty_interrupt() local 204 void __iomem *base = qtty->base; goldfish_tty_chars_in_buffer() local 300 void __iomem *base; goldfish_tty_probe() local [all...] |
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/ |
H A D | pll.c | 216 void __iomem *base = pll->base; in dss_pll_wait_reset_done() local 218 if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1) in dss_pll_wait_reset_done() 229 u32 v = readl_relaxed(pll->base + PLL_STATUS); in dss_wait_hsdiv_ack() 242 void __iomem *base = pll->base; in dss_pll_write_config_type_a() local 257 writel_relaxed(l, base + PLL_CONFIGURATION1); in dss_pll_write_config_type_a() 266 writel_relaxed(l, base + PLL_CONFIGURATION3); in dss_pll_write_config_type_a() 268 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a() 291 writel_relaxed(l, base in dss_pll_write_config_type_a() 334 void __iomem *base = pll->base; dss_pll_write_config_type_b() local [all...] |
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
H A D | channv50.c | 38 nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c, in nv50_disp_mthd_list() argument 41 struct nvkm_subdev *subdev = &disp->base.engine.subdev; in nv50_disp_mthd_list() 47 u32 next = nvkm_rd32(device, list->data[i].addr + base + 0); in nv50_disp_mthd_list() 48 u32 prev = nvkm_rd32(device, list->data[i].addr + base + c); in nv50_disp_mthd_list() 70 struct nvkm_subdev *subdev = &disp->base.engine.subdev; in nv50_disp_chan_mthd() 81 u32 base = chan->head * mthd->addr; in nv50_disp_chan_mthd() local 82 for (j = 0; j < mthd->data[i].nr; j++, base += list->addr) { in nv50_disp_chan_mthd() 100 nv50_disp_mthd_list(disp, debug, base, mthd->prev, in nv50_disp_chan_mthd() 110 struct nvkm_device *device = disp->base.engine.subdev.device; in nv50_disp_chan_uevent_fini() 119 struct nvkm_device *device = disp->base in nv50_disp_chan_uevent_init() 181 u64 size, base = chan->func->user(chan, &size); nv50_disp_chan_rd32() local 191 u64 size, base = chan->func->user(chan, &size); nv50_disp_chan_wr32() local 218 const u64 base = device->func->resource_addr(device, 0); nv50_disp_chan_map() local 231 nv50_disp_chan_child_del_(struct nvkm_oproxy *base) nv50_disp_chan_child_del_() argument [all...] |
/kernel/linux/linux-6.6/drivers/spi/ |
H A D | spi-rzv2m-csi.c | 86 void __iomem *base; member 113 tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value; in rzv2m_csi_reg_write_bit() 114 writel(tmp, csi->base + reg_offs); in rzv2m_csi_reg_write_bit() 126 return readl_poll_timeout(csi->base + CSI_MODE, reg, in rzv2m_csi_sw_reset() 141 return readl_poll_timeout(csi->base + CSI_MODE, reg, in rzv2m_csi_start_stop_operation() 150 if (readl(csi->base + CSI_OFIFOL)) in rzv2m_csi_fill_txfifo() 157 writel(buf[i], csi->base + CSI_OFIFO); in rzv2m_csi_fill_txfifo() 162 writel(buf[i], csi->base + CSI_OFIFO); in rzv2m_csi_fill_txfifo() 175 if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer) in rzv2m_csi_read_rxfifo() 182 buf[i] = (u16)readl(csi->base in rzv2m_csi_read_rxfifo() [all...] |
/kernel/linux/linux-6.6/drivers/tty/ |
H A D | goldfish.c | 39 void __iomem *base; member 59 void __iomem *base = qtty->base; in do_rw_io() local 62 gf_write_ptr((void *)address, base + GOLDFISH_TTY_REG_DATA_PTR, in do_rw_io() 63 base + GOLDFISH_TTY_REG_DATA_PTR_HIGH); in do_rw_io() 64 gf_iowrite32(count, base + GOLDFISH_TTY_REG_DATA_LEN); in do_rw_io() 68 base + GOLDFISH_TTY_REG_CMD); in do_rw_io() 71 base + GOLDFISH_TTY_REG_CMD); in do_rw_io() 139 void __iomem *base = qtty->base; in goldfish_tty_interrupt() local 203 void __iomem *base = qtty->base; goldfish_tty_chars_in_buffer() local 299 void __iomem *base; goldfish_tty_probe() local [all...] |