Lines Matching refs:base
25 void __iomem *base;
100 void __iomem *base = aspeed->base;
108 writel_relaxed(CMD_WRITE, base + OPB0_RW);
109 writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
110 writel_relaxed(addr, base + OPB0_FSI_ADDR);
111 writel_relaxed(val, base + OPB0_FSI_DATA_W);
112 writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
113 writel(0x1, base + OPB_TRIGGER);
115 ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
119 status = readl(base + OPB0_STATUS);
152 void __iomem *base = aspeed->base;
160 writel_relaxed(CMD_READ, base + OPB0_RW);
161 writel_relaxed(transfer_size, base + OPB0_XFER_SIZE);
162 writel_relaxed(addr, base + OPB0_FSI_ADDR);
163 writel_relaxed(0x1, base + OPB_IRQ_CLEAR);
164 writel(0x1, base + OPB_TRIGGER);
166 ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
170 status = readl(base + OPB0_STATUS);
172 result = readl(base + OPB0_FSI_DATA_R);
175 readl(base + OPB0_STATUS),
555 aspeed->base = devm_platform_ioremap_resource(pdev, 0);
556 if (IS_ERR(aspeed->base)) {
557 rc = PTR_ERR(aspeed->base);
578 writel(0x1, aspeed->base + OPB_CLK_SYNC);
580 aspeed->base + OPB_IRQ_MASK);
583 writel(0x10, aspeed->base + OPB_RETRY_COUNTER);
585 writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
586 writel(fsi_base, aspeed->base + OPB_FSI_BASE);
589 writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1);
592 writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1);
593 writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2);
600 writel(0x1, aspeed->base + OPB0_SELECT);