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/kernel/linux/linux-5.10/arch/x86/kernel/cpu/mtrr/
H A Dgeneric.c164 u64 base, mask; in mtrr_type_lookup_variable() local
177 base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) + in mtrr_type_lookup_variable()
182 start_state = ((start & mask) == (base & mask)); in mtrr_type_lookup_variable()
183 end_state = ((end & mask) == (base & mask)); in mtrr_type_lookup_variable()
184 inclusive = ((start < base) && (end > base)); in mtrr_type_lookup_variable()
209 *partial_end = base + get_mtrr_size(mask); in mtrr_type_lookup_variable()
211 *partial_end = base; in mtrr_type_lookup_variable()
223 if ((start & mask) != (base & mask)) in mtrr_type_lookup_variable()
372 static void __init update_fixed_last(unsigned base, unsigne argument
381 print_fixed(unsigned base, unsigned step, const mtrr_type *types) print_fixed() argument
560 generic_get_free_region(unsigned long base, unsigned long size, int replace_reg) generic_get_free_region() argument
579 generic_get_mtrr(unsigned int reg, unsigned long *base, unsigned long *size, mtrr_type *type) generic_get_mtrr() argument
831 generic_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) generic_set_mtrr() argument
863 generic_validate_add_page(unsigned long base, unsigned long size, unsigned int type) generic_validate_add_page() argument
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/kernel/linux/linux-5.10/drivers/iio/adc/
H A Dmxs-lradc-adc.c117 void __iomem *base; member
157 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
158 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
166 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
170 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
171 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
173 writel(0, adc->base + LRADC_CH(0)); in mxs_lradc_adc_read_single()
177 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
178 writel(BIT(0), adc->base in mxs_lradc_adc_read_single()
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/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-sc27xx.c107 u32 base; member
128 return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, in sprd_rtc_clear_alarm_ints()
137 ret = regmap_read(rtc->regmap, rtc->base + SPRD_RTC_SPG_VALUE, &val); in sprd_rtc_lock_alarm()
147 ret = regmap_write(rtc->regmap, rtc->base + SPRD_RTC_SPG_UPD, val); in sprd_rtc_lock_alarm()
153 rtc->base + SPRD_RTC_INT_RAW_STS, val, in sprd_rtc_lock_alarm()
162 return regmap_write(rtc->regmap, rtc->base + SPRD_RTC_INT_CLR, in sprd_rtc_lock_alarm()
196 ret = regmap_read(rtc->regmap, rtc->base + sec_reg, &val); in sprd_rtc_get_secs()
202 ret = regmap_read(rtc->regmap, rtc->base + min_reg, &val); in sprd_rtc_get_secs()
208 ret = regmap_read(rtc->regmap, rtc->base + hour_reg, &val); in sprd_rtc_get_secs()
214 ret = regmap_read(rtc->regmap, rtc->base in sprd_rtc_get_secs()
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H A Drtc-pl030.c25 void __iomem *base; member
31 writel(0, rtc->base + RTC_EOI); in pl030_interrupt()
39 rtc_time64_to_tm(readl(rtc->base + RTC_MR), &alrm->time); in pl030_read_alarm()
47 writel(rtc_tm_to_time64(&alrm->time), rtc->base + RTC_MR); in pl030_set_alarm()
56 rtc_time64_to_tm(readl(rtc->base + RTC_DR), tm); in pl030_read_time()
73 writel(rtc_tm_to_time64(tm) + 1, rtc->base + RTC_LR); in pl030_set_time()
108 rtc->base = ioremap(dev->res.start, resource_size(&dev->res)); in pl030_probe()
109 if (!rtc->base) { in pl030_probe()
114 __raw_writel(0, rtc->base + RTC_CR); in pl030_probe()
115 __raw_writel(0, rtc->base in pl030_probe()
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/kernel/linux/linux-5.10/drivers/watchdog/
H A Df71808e_wdt.c130 static inline int superio_inb(int base, int reg);
131 static inline int superio_inw(int base, int reg);
132 static inline void superio_outb(int base, int reg, u8 val);
133 static inline void superio_set_bit(int base, int reg, int bit);
134 static inline void superio_clear_bit(int base, int reg, int bit);
135 static inline int superio_enter(int base);
136 static inline void superio_select(int base, int ld);
137 static inline void superio_exit(int base);
160 static inline int superio_inb(int base, int reg) in superio_inb() argument
162 outb(reg, base); in superio_inb()
166 superio_inw(int base, int reg) superio_inw() argument
174 superio_outb(int base, int reg, u8 val) superio_outb() argument
180 superio_set_bit(int base, int reg, int bit) superio_set_bit() argument
187 superio_clear_bit(int base, int reg, int bit) superio_clear_bit() argument
194 superio_enter(int base) superio_enter() argument
209 superio_select(int base, int ld) superio_select() argument
215 superio_exit(int base) superio_exit() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dp_hdcp.c35 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_write_an_aksv()
70 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_read_bksv()
86 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_read_bstatus()
108 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_dp_hdcp_read_bcaps()
141 struct drm_i915_private *i915 = to_i915(dig_port->base.base in intel_dp_hdcp_read_ri_prime()
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/kernel/linux/linux-6.6/drivers/fsi/
H A Dfsi-master-aspeed.c25 void __iomem *base; member
100 void __iomem *base = aspeed->base; in __opb_write() local
108 writel_relaxed(CMD_WRITE, base + OPB0_RW); in __opb_write()
109 writel_relaxed(transfer_size, base + OPB0_XFER_SIZE); in __opb_write()
110 writel_relaxed(addr, base + OPB0_FSI_ADDR); in __opb_write()
111 writel_relaxed(val, base + OPB0_FSI_DATA_W); in __opb_write()
112 writel_relaxed(0x1, base + OPB_IRQ_CLEAR); in __opb_write()
113 writel(0x1, base + OPB_TRIGGER); in __opb_write()
115 ret = readl_poll_timeout(base in __opb_write()
152 void __iomem *base = aspeed->base; __opb_read() local
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/kernel/linux/linux-6.6/drivers/iio/adc/
H A Dmxs-lradc-adc.c117 void __iomem *base; member
157 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
158 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
163 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
166 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
170 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR); in mxs_lradc_adc_read_single()
171 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
173 writel(0, adc->base + LRADC_CH(0)); in mxs_lradc_adc_read_single()
177 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET); in mxs_lradc_adc_read_single()
178 writel(BIT(0), adc->base in mxs_lradc_adc_read_single()
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/third_party/node/deps/v8/src/wasm/
H A Dstreaming-decoder.cc7 #include "src/base/platform/wrappers.h"
36 void OnBytesReceived(base::Vector<const uint8_t> bytes) override;
59 base::Vector<const uint8_t> length_bytes) in SectionBuffer()
62 bytes_(base::OwnedVector<uint8_t>::NewForOverwrite( in SectionBuffer()
73 base::Vector<const uint8_t> GetCode(WireBytesRef ref) const final {
80 base::Optional<ModuleWireBytes> GetModuleBytes() const final { return {}; }
83 base::Vector<uint8_t> bytes() const { return bytes_.as_vector(); } in bytes()
84 base::Vector<uint8_t> payload() const { return bytes() + payload_offset_; } in payload()
90 const base::OwnedVector<uint8_t> bytes_;
127 base
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/third_party/mesa3d/src/virtio/vulkan/
H A Dvn_image.c231 vn_object_base_init(&img->base, VK_OBJECT_TYPE_IMAGE, &dev->base); in vn_image_create()
235 vn_object_base_fini(&img->base); in vn_image_create()
269 vn_object_base_init(&img->base, VK_OBJECT_TYPE_IMAGE, &dev->base); in vn_image_create_deferred()
273 vn_object_base_fini(&img->base); in vn_image_create_deferred()
294 pAllocator ? pAllocator : &dev->base.base.alloc; in vn_CreateImage()
350 pAllocator ? pAllocator : &dev->base.base in vn_DestroyImage()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/
H A Dnv30_screen.c525 struct nouveau_pushbuf *push = screen->base.pushbuf; in nv30_screen_fence_emit()
527 *sequence = ++screen->base.fence.sequence; in nv30_screen_fence_emit()
549 if (!nouveau_drm_screen_unref(&screen->base)) in nv30_screen_destroy()
552 nouveau_fence_cleanup(&screen->base); in nv30_screen_destroy()
571 nouveau_screen_fini(&screen->base); in nv30_screen_destroy()
578 screen->base.base.context_create = NULL; \
579 return &screen->base; \
627 pscreen = &screen->base.base; in nv30_screen_create()
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/third_party/node/deps/v8/src/heap/
H A Dmemory-allocator.cc9 #include "src/base/address-region.h"
189 base::MutexGuard guard(&mutex_); in NumberOfCommittedChunks()
195 base::MutexGuard guard(&mutex_); in NumberOfChunks()
204 base::MutexGuard guard(&mutex_); in CommittedBufferedMemory()
219 Address base = reservation->address(); in CommitMemory() local
221 if (!reservation->SetPermissions(base, size, PageAllocator::kReadWrite)) { in CommitMemory()
224 UpdateAllocatedSpaceLimits(base, base + size); in CommitMemory()
238 Address base, size_t size) { in FreeMemoryRegion()
239 FreePages(page_allocator, reinterpret_cast<void*>(base), siz in FreeMemoryRegion()
237 FreeMemoryRegion(v8::PageAllocator* page_allocator, Address base, size_t size) FreeMemoryRegion() argument
264 Address base = reservation.address(); AllocateAlignedMemory() local
357 Address base = AllocateUninitializedChunk() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c892 return &dpp->base; in dcn30_dpp_create()
912 return &opp->base; in dcn30_opp_create()
932 return &aux_engine->base; in dcn30_aux_engine_create()
988 return &mpc30->base; in dcn30_mpc_create()
1017 return &hubbub3->base; in dcn30_hubbub_create()
1030 tgn10->base.inst = instance; in dcn30_timing_generator_create()
1031 tgn10->base.ctx = ctx; in dcn30_timing_generator_create()
1039 return &tgn10->base; in dcn30_timing_generator_create()
1072 return &enc20->enc10.base; in dcn30_link_encoder_create()
1089 return &panel_cntl->base; in dcn30_panel_cntl_create()
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/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_context.cpp510 cso->base = *rs_state; in d3d12_create_rasterizer_state()
517 cso->base.cull_face = PIPE_FACE_BACK; in d3d12_create_rasterizer_state()
809 struct pipe_sampler_view *state = &sampler_view->base; in d3d12_init_sampler_view_descriptor()
837 assert(offset == 0 || res->base.b.target == PIPE_BUFFER); in d3d12_init_sampler_view_descriptor()
932 sampler_view->base = *state; in d3d12_create_sampler_view()
933 sampler_view->base.texture = NULL; in d3d12_create_sampler_view()
934 pipe_resource_reference(&sampler_view->base.texture, texture); in d3d12_create_sampler_view()
935 sampler_view->base.reference.count = 1; in d3d12_create_sampler_view()
936 sampler_view->base.context = pctx; in d3d12_create_sampler_view()
943 format_info.swizzle[sampler_view->base in d3d12_create_sampler_view()
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/kernel/linux/linux-6.6/drivers/net/can/
H A Dsun4i_can.c67 /* Registers address (physical base address 0x01C2BC00) */
218 void __iomem *base; member
242 writel(val, priv->base + SUN4I_REG_CMD_ADDR); in sun4i_can_write_cmdreg()
253 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); in set_normal_mode()
255 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); in set_normal_mode()
258 if (readl(priv->base + SUN4I_REG_MSEL_ADDR) & SUN4I_MSEL_RESET_MODE) { in set_normal_mode()
274 mod_reg_val = readl(priv->base + SUN4I_REG_MSEL_ADDR); in set_reset_mode()
276 writel(mod_reg_val, priv->base + SUN4I_REG_MSEL_ADDR); in set_reset_mode()
279 if (!(readl(priv->base + SUN4I_REG_MSEL_ADDR) & in set_reset_mode()
303 writel(cfg, priv->base in sun4ican_set_bittiming()
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/kernel/linux/linux-6.6/drivers/thermal/mediatek/
H A Dlvts_thermal.c120 void __iomem *base; member
133 void __iomem *base; member
143 void __iomem *base; member
223 regset->base = lvts_ctrl->base; in lvts_debugfs_init()
320 value = readl(LVTS_MONINT(lvts_ctrl->base)); in lvts_update_irq_mask()
330 writel(value, LVTS_MONINT(lvts_ctrl->base)); in lvts_update_irq_mask()
352 void __iomem *base = lvts_sensor->base; in lvts_set_trips() local
381 writel(raw_low, LVTS_OFFSETL(base)); in lvts_set_trips()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c56 container_of(clk_mgr, struct clk_mgr_vgh, base)
157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks()
563 struct clk_bw_params *bw_params = clk_mgr->base.bw_params; in vg_clk_mgr_helper_populate_bw_params()
667 clk_mgr->base.base.ctx = ctx; in vg_clk_mgr_construct()
668 clk_mgr->base.base.funcs = &vg_funcs; in vg_clk_mgr_construct()
670 clk_mgr->base.pp_smu = pp_smu; in vg_clk_mgr_construct()
672 clk_mgr->base in vg_clk_mgr_construct()
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/third_party/mesa3d/src/gallium/drivers/r300/
H A Dr300_texture.c991 struct r300_resource *tex = r300_resource(surf->base.texture); in r300_texture_setup_fb_state()
992 unsigned level = surf->base.u.tex.level; in r300_texture_setup_fb_state()
994 r300_stride_to_width(surf->base.format, tex->tex.stride_in_bytes[level]); in r300_texture_setup_fb_state()
997 if (util_format_is_depth_or_stencil(surf->base.format)) { in r300_texture_setup_fb_state()
1002 R300_DEPTHENDIAN(r300_get_endian_swap(surf->base.format)); in r300_texture_setup_fb_state()
1003 surf->format = r300_translate_zsformat(surf->base.format); in r300_texture_setup_fb_state()
1007 enum pipe_format format = util_format_linear(surf->base.format); in r300_texture_setup_fb_state()
1044 const struct pipe_resource *base, in r300_texture_create_object()
1061 tex->b.usage = base->usage; in r300_texture_create_object()
1062 tex->b.bind = base in r300_texture_create_object()
1043 r300_texture_create_object(struct r300_screen *rscreen, const struct pipe_resource *base, enum radeon_bo_layout microtile, enum radeon_bo_layout macrotile, unsigned stride_in_bytes_override, struct pb_buffer *buffer) r300_texture_create_object() argument
1129 r300_texture_create(struct pipe_screen *screen, const struct pipe_resource *base) r300_texture_create() argument
1150 r300_texture_from_handle(struct pipe_screen *screen, const struct pipe_resource *base, struct winsys_handle *whandle, unsigned usage) r300_texture_from_handle() argument
[all...]
/third_party/skia/third_party/externals/abseil-cpp/absl/strings/
H A Dnumbers.cc33 #include "absl/base/attributes.h"
34 #include "absl/base/internal/raw_logging.h"
361 // into a base-10 exponent and 6 ASCII digits, where the first digit is never
372 // in the output ASCII array, and exp is the base-10 exponent. It would be in SplitToSix()
373 // faster to use a table here, and to look up the base-2 exponent of value, in SplitToSix()
434 // track the base-2 exponent of both sides. This greatly simplifies the in SplitToSix()
642 int base = *base_ptr; in safe_parse_sign_and_base() local
664 // Consume base-dependent prefix. in safe_parse_sign_and_base()
665 // base 0: "0x" -> base 1 in safe_parse_sign_and_base()
917 safe_parse_positive_int(absl::string_view text, int base, IntType* value_p) safe_parse_positive_int() argument
953 safe_parse_negative_int(absl::string_view text, int base, IntType* value_p) safe_parse_negative_int() argument
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/kernel/linux/linux-5.10/crypto/
H A Dakcipher.c64 akcipher->base.exit = crypto_akcipher_exit_tfm; in crypto_akcipher_init_tfm()
90 .tfmsize = offsetof(struct crypto_akcipher, base),
97 spawn->base.frontend = &crypto_akcipher_type; in crypto_grab_akcipher()
98 return crypto_grab_spawn(&spawn->base, inst, name, type, mask); in crypto_grab_akcipher()
111 struct crypto_alg *base = &alg->base; in akcipher_prepare_alg() local
113 base->cra_type = &crypto_akcipher_type; in akcipher_prepare_alg()
114 base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; in akcipher_prepare_alg()
115 base->cra_flags |= CRYPTO_ALG_TYPE_AKCIPHER; in akcipher_prepare_alg()
131 struct crypto_alg *base in crypto_register_akcipher() local
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/kernel/linux/linux-5.10/drivers/char/hw_random/
H A Dingenic-trng.c33 void __iomem *base; member
43 ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_init()
45 writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_init()
55 ctrl = readl(trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_cleanup()
57 writel(ctrl, trng->base + TRNG_REG_CFG_OFFSET); in ingenic_trng_cleanup()
67 ret = readl_poll_timeout(trng->base + TRNG_REG_STATUS_OFFSET, status, in ingenic_trng_read()
74 *data = readl(trng->base + TRNG_REG_RANDOMNUM_OFFSET); in ingenic_trng_read()
88 trng->base = devm_platform_ioremap_resource(pdev, 0); in ingenic_trng_probe()
89 if (IS_ERR(trng->base)) { in ingenic_trng_probe()
91 ret = PTR_ERR(trng->base); in ingenic_trng_probe()
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/kernel/linux/linux-5.10/drivers/net/mdio/
H A Dmdio-ipq8064.c39 struct regmap *base; /* NSS_GMAC0_BASE */ member
47 return regmap_read_poll_timeout(priv->base, MII_ADDR_REG_ADDR, busy, in ipq8064_mdio_wait_busy()
67 regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); in ipq8064_mdio_read()
74 regmap_read(priv->base, MII_DATA_REG_ADDR, &ret_val); in ipq8064_mdio_read()
88 regmap_write(priv->base, MII_DATA_REG_ADDR, data); in ipq8064_mdio_write()
93 regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); in ipq8064_mdio_write()
117 void __iomem *base; in ipq8064_mdio_probe() local
123 base = ioremap(res.start, resource_size(&res)); in ipq8064_mdio_probe()
124 if (!base) in ipq8064_mdio_probe()
138 priv->base in ipq8064_mdio_probe()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv50.c94 nv50_devinit_preinit(struct nvkm_devinit *base) in nv50_devinit_preinit() argument
96 struct nvkm_subdev *subdev = &base->subdev; in nv50_devinit_preinit()
103 if (!base->post) { in nv50_devinit_preinit()
104 u64 disable = nvkm_devinit_disable(base); in nv50_devinit_preinit()
106 base->post = true; in nv50_devinit_preinit()
112 if (!base->post) { in nv50_devinit_preinit()
116 base->post = true; in nv50_devinit_preinit()
122 nv50_devinit_init(struct nvkm_devinit *base) in nv50_devinit_init() argument
124 struct nv50_devinit *init = nv50_devinit(base); in nv50_devinit_init()
125 struct nvkm_subdev *subdev = &init->base in nv50_devinit_init()
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/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-lpc32xx.c20 void __iomem *base; member
54 val = readl(lpc32xx->base); in lpc32xx_pwm_config()
57 writel(val, lpc32xx->base); in lpc32xx_pwm_config()
72 val = readl(lpc32xx->base); in lpc32xx_pwm_enable()
74 writel(val, lpc32xx->base); in lpc32xx_pwm_enable()
84 val = readl(lpc32xx->base); in lpc32xx_pwm_disable()
86 writel(val, lpc32xx->base); in lpc32xx_pwm_disable()
110 lpc32xx->base = devm_ioremap_resource(&pdev->dev, res); in lpc32xx_pwm_probe()
111 if (IS_ERR(lpc32xx->base)) in lpc32xx_pwm_probe()
112 return PTR_ERR(lpc32xx->base); in lpc32xx_pwm_probe()
[all...]
/kernel/linux/linux-5.10/drivers/regulator/
H A Dstm32-pwr.c42 void __iomem *base; member
51 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_is_ready()
61 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_is_enabled()
72 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_enable()
74 writel_relaxed(val, priv->base + REG_PWR_CR3); in stm32_pwr_reg_enable()
91 val = readl_relaxed(priv->base + REG_PWR_CR3); in stm32_pwr_reg_disable()
93 writel_relaxed(val, priv->base + REG_PWR_CR3); in stm32_pwr_reg_disable()
133 void __iomem *base; in stm32_pwr_regulator_probe() local
138 base = devm_platform_ioremap_resource(pdev, 0); in stm32_pwr_regulator_probe()
139 if (IS_ERR(base)) { in stm32_pwr_regulator_probe()
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