Home
last modified time | relevance | path

Searched refs:base (Results 1051 - 1075 of 17150) sorted by relevance

1...<<41424344454647484950>>...686

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c37 cp110->base.ctx->logger
101 return cp110->base.raw_size * cp110->base.banks_num * in lpt_size_alignment()
102 cp110->base.dram_channels_num; in lpt_size_alignment()
109 if (cp110->base.options.bits.LPT_MC_CONFIG == 1) { in lpt_memory_control_config()
117 switch (cp110->base.dram_channels_num) { in lpt_memory_control_config()
148 switch (cp110->base.banks_num) { in lpt_memory_control_config()
195 switch (cp110->base.channel_interleave_size) { in lpt_memory_control_config()
231 switch (cp110->base.raw_size) { in lpt_memory_control_config()
273 if (cp110->base in is_source_bigger_than_epanel_size()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_crtc.c42 crtc->base.id, crtc->name)) in assert_vblank_disabled()
66 drm_crtc_wait_one_vblank(&crtc->base); in intel_crtc_wait_for_next_vblank()
80 struct drm_device *dev = crtc->base.dev; in intel_crtc_get_vblank_counter()
81 struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; in intel_crtc_get_vblank_counter()
87 return (u32)drm_crtc_accurate_vblank_count(&crtc->base); in intel_crtc_get_vblank_counter()
89 return crtc->base.funcs->get_vblank_counter(&crtc->base); in intel_crtc_get_vblank_counter()
126 assert_vblank_disabled(&crtc->base); in intel_crtc_vblank_on()
127 drm_crtc_set_max_vblank_count(&crtc->base, in intel_crtc_vblank_on()
129 drm_crtc_vblank_on(&crtc->base); in intel_crtc_vblank_on()
400 intel_crtc_vblank_work(struct kthread_work *base) intel_crtc_vblank_work() argument
[all...]
/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-sprd.c81 void __iomem *base; member
95 writel(count, i2c_dev->base + I2C_COUNT); in sprd_i2c_set_count()
100 u32 tmp = readl(i2c_dev->base + I2C_CTL); in sprd_i2c_send_stop()
103 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL); in sprd_i2c_send_stop()
105 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL); in sprd_i2c_send_stop()
110 u32 tmp = readl(i2c_dev->base + I2C_CTL); in sprd_i2c_clear_start()
112 writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL); in sprd_i2c_clear_start()
117 u32 tmp = readl(i2c_dev->base + I2C_STATUS); in sprd_i2c_clear_ack()
119 writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS); in sprd_i2c_clear_ack()
124 u32 tmp = readl(i2c_dev->base in sprd_i2c_clear_irq()
[all...]
/third_party/node/deps/v8/src/diagnostics/s390/
H A Ddisasm-s390.cc14 // v8::base::EmbeddedVector<char, 256> buffer;
32 #include "src/base/platform/platform.h"
33 #include "src/base/strings.h"
34 #include "src/base/vector.h"
50 Decoder(const disasm::NameConverter& converter, base::Vector<char> out_buffer) in Decoder()
89 base::Vector<char> out_buffer_;
133 base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d - 0x%x", in PrintSoftwareInterrupt()
137 base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", svc); in PrintSoftwareInterrupt()
260 base::SNPrintF(out_buffer_ + out_buffer_pos_, "%d", value); in FormatOption()
282 out_buffer_pos_ += base in FormatOption()
[all...]
/kernel/linux/linux-5.10/arch/powerpc/include/asm/
H A Ddcr-native.h18 unsigned int base; member
27 ((dcr_host_native_t){ .base = (dcr_n) })
29 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
30 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
130 #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
131 DCRN_ ## base ## _CONFIG_DATA, \
134 #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
135 DCRN_ ## base ## _CONFIG_DAT
[all...]
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-owl.c34 static inline void owl_timer_reset(void __iomem *base) in owl_timer_reset() argument
36 writel(0, base + OWL_Tx_CTL); in owl_timer_reset()
37 writel(0, base + OWL_Tx_VAL); in owl_timer_reset()
38 writel(0, base + OWL_Tx_CMP); in owl_timer_reset()
41 static inline void owl_timer_set_enabled(void __iomem *base, bool enabled) in owl_timer_set_enabled() argument
43 u32 ctl = readl(base + OWL_Tx_CTL); in owl_timer_set_enabled()
53 writel(ctl, base + OWL_Tx_CTL); in owl_timer_set_enabled()
83 void __iomem *base = owl_clkevt_base; in owl_timer_set_next_event() local
85 owl_timer_set_enabled(base, false); in owl_timer_set_next_event()
86 writel(OWL_Tx_CTL_INTEN, base in owl_timer_set_next_event()
[all...]
/kernel/linux/linux-6.6/arch/powerpc/include/asm/
H A Ddcr-native.h18 unsigned int base; member
27 ((dcr_host_native_t){ .base = (dcr_n) })
29 #define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base)
30 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
130 #define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \
131 DCRN_ ## base ## _CONFIG_DATA, \
134 #define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \
135 DCRN_ ## base ## _CONFIG_DAT
[all...]
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dirq-gic-common.c61 void __iomem *base, void (*sync_access)(void)) in gic_configure_irq()
74 val = oldval = readl_relaxed(base + confoff); in gic_configure_irq()
94 writel_relaxed(val, base + confoff); in gic_configure_irq()
95 if (readl_relaxed(base + confoff) != val) in gic_configure_irq()
106 void gic_dist_config(void __iomem *base, int gic_irqs, in gic_dist_config() argument
116 base + GIC_DIST_CONFIG + i / 4); in gic_dist_config()
122 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config()
130 base + GIC_DIST_ACTIVE_CLEAR + i / 8); in gic_dist_config()
132 base + GIC_DIST_ENABLE_CLEAR + i / 8); in gic_dist_config()
139 void gic_cpu_config(void __iomem *base, in argument
60 gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) gic_configure_irq() argument
[all...]
/kernel/linux/linux-5.10/drivers/thermal/
H A Dtango_thermal.c29 void __iomem *base; member
33 static bool temp_above_thresh(void __iomem *base, int thresh_idx) in temp_above_thresh() argument
35 writel(CMD_READ | thresh_idx << 8, base + TEMPSI_CMD); in temp_above_thresh()
37 writel(CMD_READ | thresh_idx << 8, base + TEMPSI_CMD); in temp_above_thresh()
39 return readl(base + TEMPSI_RES); in temp_above_thresh()
47 if (temp_above_thresh(priv->base, idx)) { in tango_get_temp()
49 while (idx < IDX_MAX && temp_above_thresh(priv->base, ++idx)) in tango_get_temp()
54 while (idx > IDX_MIN && !temp_above_thresh(priv->base, --idx)) in tango_get_temp()
70 writel(0, priv->base + TEMPSI_CFG); in tango_thermal_init()
71 writel(CMD_ON, priv->base in tango_thermal_init()
[all...]
/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-aspeed.c12 void __iomem *base; member
28 if (!(readl(rtc->base + RTC_CTRL) & RTC_ENABLE)) { in aspeed_rtc_read_time()
34 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
36 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
68 ctrl = readl(rtc->base + RTC_CTRL); in aspeed_rtc_set_time()
69 writel(ctrl | RTC_UNLOCK, rtc->base + RTC_CTRL); in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
72 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
75 writel(ctrl | RTC_ENABLE, rtc->base in aspeed_rtc_set_time()
[all...]
/kernel/linux/linux-5.10/include/crypto/
H A Dacompress.h18 * @base: Common attributes for asynchronous crypto requests
27 struct crypto_async_request base; member
45 * @base: Common crypto API algorithm data structure
52 struct crypto_tfm base; member
74 * @base: Common crypto API algorithm data structure
83 struct crypto_alg base; member
130 return &tfm->base; in crypto_acomp_tfm()
135 return container_of(alg, struct acomp_alg, base); in __crypto_acomp_alg()
140 return container_of(tfm, struct crypto_acomp, base); in __crypto_acomp_tfm()
156 req->base in acomp_request_set_tfm()
[all...]
/kernel/linux/linux-6.6/drivers/rtc/
H A Drtc-aspeed.c12 void __iomem *base; member
28 if (!(readl(rtc->base + RTC_CTRL) & RTC_ENABLE)) { in aspeed_rtc_read_time()
34 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
35 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
36 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
68 ctrl = readl(rtc->base + RTC_CTRL); in aspeed_rtc_set_time()
69 writel(ctrl | RTC_UNLOCK, rtc->base + RTC_CTRL); in aspeed_rtc_set_time()
71 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
72 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
75 writel(ctrl | RTC_ENABLE, rtc->base in aspeed_rtc_set_time()
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-owl.c34 static inline void owl_timer_reset(void __iomem *base) in owl_timer_reset() argument
36 writel(0, base + OWL_Tx_CTL); in owl_timer_reset()
37 writel(0, base + OWL_Tx_VAL); in owl_timer_reset()
38 writel(0, base + OWL_Tx_CMP); in owl_timer_reset()
41 static inline void owl_timer_set_enabled(void __iomem *base, bool enabled) in owl_timer_set_enabled() argument
43 u32 ctl = readl(base + OWL_Tx_CTL); in owl_timer_set_enabled()
53 writel(ctl, base + OWL_Tx_CTL); in owl_timer_set_enabled()
83 void __iomem *base = owl_clkevt_base; in owl_timer_set_next_event() local
85 owl_timer_set_enabled(base, false); in owl_timer_set_next_event()
86 writel(OWL_Tx_CTL_INTEN, base in owl_timer_set_next_event()
[all...]
/kernel/linux/linux-6.6/arch/x86/crypto/
H A Dtwofish_glue_3way.c24 return twofish_setkey(&tfm->base, key, keylen); in twofish_setkey_skcipher()
78 .base.cra_name = "ecb(twofish)",
79 .base.cra_driver_name = "ecb-twofish-3way",
80 .base.cra_priority = 300,
81 .base.cra_blocksize = TF_BLOCK_SIZE,
82 .base.cra_ctxsize = sizeof(struct twofish_ctx),
83 .base.cra_module = THIS_MODULE,
90 .base.cra_name = "cbc(twofish)",
91 .base.cra_driver_name = "cbc-twofish-3way",
92 .base
[all...]
/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-gic-common.c48 void __iomem *base, void (*sync_access)(void)) in gic_configure_irq()
61 val = oldval = readl_relaxed(base + confoff); in gic_configure_irq()
81 writel_relaxed(val, base + confoff); in gic_configure_irq()
82 if (readl_relaxed(base + confoff) != val) in gic_configure_irq()
93 void gic_dist_config(void __iomem *base, int gic_irqs, in gic_dist_config() argument
103 base + GIC_DIST_CONFIG + i / 4); in gic_dist_config()
109 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config()
117 base + GIC_DIST_ACTIVE_CLEAR + i / 8); in gic_dist_config()
119 base + GIC_DIST_ENABLE_CLEAR + i / 8); in gic_dist_config()
126 void gic_cpu_config(void __iomem *base, in argument
47 gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) gic_configure_irq() argument
[all...]
/kernel/liteos_a/kernel/base/misc/
H A Dswtmr_shellcmd.c131 SwtmrDebugBase *base = &data.base; in OsSwtmrTimeInfoShow() local
132 UINT64 waitTime = ((base->waitTime / base->waitCount) * OS_NS_PER_CYCLE) / OS_SYS_NS_PER_US; in OsSwtmrTimeInfoShow()
133 UINT64 waitTimeMax = (base->waitTimeMax * OS_NS_PER_CYCLE) / OS_SYS_NS_PER_US; in OsSwtmrTimeInfoShow()
134 UINT64 runTime = ((base->runTime / base->runCount) * OS_NS_PER_CYCLE) / OS_SYS_NS_PER_US; in OsSwtmrTimeInfoShow()
135 UINT64 runTimeMax = (base->runTimeMax * OS_NS_PER_CYCLE) / OS_SYS_NS_PER_US; in OsSwtmrTimeInfoShow()
136 UINT64 readyTime = ((base->readyTime / base in OsSwtmrTimeInfoShow()
[all...]
/third_party/jerryscript/tests/jerry/es2015/
H A Dfunction-prototype-hasinstance.js15 function base (value) { class
19 base.prototype.method = function () { return this.member; }
25 sub.prototype = base;
28 var obj_base = new base (3);
31 assert (base[Symbol.hasInstance] (obj_base) === true);
32 assert (base[Symbol.hasInstance] (obj_sub) === false);
45 sub_c.prototype = Object.create (base.prototype)
50 assert (base[Symbol.hasInstance] (obj_sub_c) === true);
59 assert (base[Symbol.hasInstance] (3) === false);
65 assert (base[Symbo
[all...]
/kernel/linux/linux-5.10/drivers/staging/media/ipu3/
H A Dipu3-css.c203 static int imgu_hw_wait(void __iomem *base, int reg, u32 mask, u32 cmp) in imgu_hw_wait() argument
207 return readl_poll_timeout(base + reg, val, (val & mask) == cmp, in imgu_hw_wait()
213 int imgu_css_set_powerup(struct device *dev, void __iomem *base, in imgu_css_set_powerup() argument
220 readl(base + IMGU_REG_GP_BUSY); in imgu_css_set_powerup()
221 writel(0, base + IMGU_REG_GP_BUSY); in imgu_css_set_powerup()
224 if (imgu_hw_wait(base, IMGU_REG_STATE, IMGU_STATE_IDLE_STS, in imgu_css_set_powerup()
231 writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_RESET, in imgu_css_set_powerup()
232 base + IMGU_REG_PM_CTRL); in imgu_css_set_powerup()
238 pm_ctrl = readl(base + IMGU_REG_PM_CTRL); in imgu_css_set_powerup()
239 state = readl(base in imgu_css_set_powerup()
303 imgu_css_set_powerdown(struct device *dev, void __iomem *base) imgu_css_set_powerdown() argument
328 void __iomem *const base = css->base; imgu_css_hw_enable_irq() local
426 void __iomem *const base = css->base; imgu_css_hw_init() local
484 void __iomem *const base = css->base; imgu_css_hw_start_sp() local
529 void __iomem *const base = css->base; imgu_css_hw_start() local
622 void __iomem *const base = css->base; imgu_css_hw_stop() local
642 void __iomem *const base = css->base; imgu_css_hw_cleanup() local
1073 void __iomem *const base = css->base; imgu_css_queue_pos() local
1087 void __iomem *const base = css->base; imgu_css_queue_data() local
1125 void __iomem *const base = css->base; imgu_css_dequeue_data() local
1515 imgu_css_init(struct device *dev, struct imgu_css *css, void __iomem *base, int length) imgu_css_init() argument
2332 void __iomem *const base = css->base; imgu_css_irq_ack() local
[all...]
/kernel/linux/linux-6.6/drivers/staging/media/ipu3/
H A Dipu3-css.c190 static int imgu_hw_wait(void __iomem *base, int reg, u32 mask, u32 cmp) in imgu_hw_wait() argument
194 return readl_poll_timeout(base + reg, val, (val & mask) == cmp, in imgu_hw_wait()
200 int imgu_css_set_powerup(struct device *dev, void __iomem *base, in imgu_css_set_powerup() argument
207 readl(base + IMGU_REG_GP_BUSY); in imgu_css_set_powerup()
208 writel(0, base + IMGU_REG_GP_BUSY); in imgu_css_set_powerup()
211 if (imgu_hw_wait(base, IMGU_REG_STATE, IMGU_STATE_IDLE_STS, in imgu_css_set_powerup()
218 writel(readl(base + IMGU_REG_PM_CTRL) | IMGU_PM_CTRL_FORCE_RESET, in imgu_css_set_powerup()
219 base + IMGU_REG_PM_CTRL); in imgu_css_set_powerup()
225 pm_ctrl = readl(base + IMGU_REG_PM_CTRL); in imgu_css_set_powerup()
226 state = readl(base in imgu_css_set_powerup()
290 imgu_css_set_powerdown(struct device *dev, void __iomem *base) imgu_css_set_powerdown() argument
315 void __iomem *const base = css->base; imgu_css_hw_enable_irq() local
413 void __iomem *const base = css->base; imgu_css_hw_init() local
471 void __iomem *const base = css->base; imgu_css_hw_start_sp() local
516 void __iomem *const base = css->base; imgu_css_hw_start() local
609 void __iomem *const base = css->base; imgu_css_hw_stop() local
629 void __iomem *const base = css->base; imgu_css_hw_cleanup() local
1060 void __iomem *const base = css->base; imgu_css_queue_pos() local
1074 void __iomem *const base = css->base; imgu_css_queue_data() local
1112 void __iomem *const base = css->base; imgu_css_dequeue_data() local
1500 imgu_css_init(struct device *dev, struct imgu_css *css, void __iomem *base, int length) imgu_css_init() argument
2317 void __iomem *const base = css->base; imgu_css_irq_ack() local
[all...]
/kernel/linux/linux-5.10/drivers/net/can/ifi_canfd/
H A Difi_canfd.c223 void __iomem *base; member
245 priv->base + IFI_CANFD_IRQMASK); in ifi_canfd_irq_enable()
260 rxdlc = readl(priv->base + IFI_CANFD_RXFIFO_DLC); in ifi_canfd_read_fifo()
278 rxid = readl(priv->base + IFI_CANFD_RXFIFO_ID); in ifi_canfd_read_fifo()
310 readl(priv->base + IFI_CANFD_RXFIFO_DATA + i); in ifi_canfd_read_fifo()
315 writel(IFI_CANFD_RXSTCMD_REMOVE_MSG, priv->base + IFI_CANFD_RXSTCMD); in ifi_canfd_read_fifo()
316 writel(rx_irq_mask, priv->base + IFI_CANFD_INTERRUPT); in ifi_canfd_read_fifo()
330 rxst = readl(priv->base + IFI_CANFD_RXSTCMD); in ifi_canfd_do_rx_poll()
345 rxst = readl(priv->base + IFI_CANFD_RXSTCMD); in ifi_canfd_do_rx_poll()
383 u32 errctr = readl(priv->base in ifi_canfd_handle_lec_err()
[all...]
/kernel/linux/linux-5.10/drivers/hwmon/
H A Dnpcm750-pwm-fan.c19 #define NPCM7XX_PWM_REG_BASE(base, n) ((base) + ((n) * 0x1000L))
21 #define NPCM7XX_PWM_REG_PR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x00)
22 #define NPCM7XX_PWM_REG_CSR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x04)
23 #define NPCM7XX_PWM_REG_CR(base, n) (NPCM7XX_PWM_REG_BASE(base, n) + 0x08)
24 #define NPCM7XX_PWM_REG_CNRx(base, n, ch) \
25 (NPCM7XX_PWM_REG_BASE(base,
[all...]
/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-aspeed.c146 void __iomem *base; member
148 /* Synchronizes I/O mem access to base. */
182 command = readl(bus->base + ASPEED_I2C_CMD_REG); in aspeed_i2c_recover_bus()
192 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); in aspeed_i2c_recover_bus()
204 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & in aspeed_i2c_recover_bus()
215 bus->base + ASPEED_I2C_CMD_REG); in aspeed_i2c_recover_bus()
227 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & in aspeed_i2c_recover_bus()
292 command = readl(bus->base + ASPEED_I2C_CMD_REG); in aspeed_i2c_slave_irq()
298 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; in aspeed_i2c_slave_irq()
317 writel(value, bus->base in aspeed_i2c_slave_irq()
[all...]
/kernel/linux/linux-5.10/drivers/usb/host/
H A Dpci-quirks.c640 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) in uhci_reset_hc() argument
652 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); in uhci_reset_hc()
655 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) in uhci_reset_hc()
661 outw(0, base + UHCI_USBINTR); in uhci_reset_hc()
662 outw(0, base + UHCI_USBCMD); in uhci_reset_hc()
672 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) in uhci_check_and_reset_hc() argument
694 cmd = inw(base + UHCI_USBCMD); in uhci_check_and_reset_hc()
702 intr = inw(base + UHCI_USBINTR); in uhci_check_and_reset_hc()
712 uhci_reset_hc(pdev, base); in uhci_check_and_reset_hc()
728 unsigned long base in quirk_usb_handoff_uhci() local
751 void __iomem *base; quirk_usb_handoff_ohci() local
931 void __iomem *base, *op_reg_base; quirk_usb_disable_ehci() local
1145 void __iomem *base; quirk_usb_handoff_xhci() local
[all...]
/kernel/linux/linux-6.6/drivers/net/can/ifi_canfd/
H A Difi_canfd.c223 void __iomem *base; member
245 priv->base + IFI_CANFD_IRQMASK); in ifi_canfd_irq_enable()
260 rxdlc = readl(priv->base + IFI_CANFD_RXFIFO_DLC); in ifi_canfd_read_fifo()
278 rxid = readl(priv->base + IFI_CANFD_RXFIFO_ID); in ifi_canfd_read_fifo()
310 readl(priv->base + IFI_CANFD_RXFIFO_DATA + i); in ifi_canfd_read_fifo()
318 writel(IFI_CANFD_RXSTCMD_REMOVE_MSG, priv->base + IFI_CANFD_RXSTCMD); in ifi_canfd_read_fifo()
319 writel(rx_irq_mask, priv->base + IFI_CANFD_INTERRUPT); in ifi_canfd_read_fifo()
330 rxst = readl(priv->base + IFI_CANFD_RXSTCMD); in ifi_canfd_do_rx_poll()
345 rxst = readl(priv->base + IFI_CANFD_RXSTCMD); in ifi_canfd_do_rx_poll()
380 u32 errctr = readl(priv->base in ifi_canfd_handle_lec_err()
[all...]
/kernel/linux/linux-6.6/drivers/usb/host/
H A Dpci-quirks.c638 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) in uhci_reset_hc() argument
650 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); in uhci_reset_hc()
653 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) in uhci_reset_hc()
659 outw(0, base + UHCI_USBINTR); in uhci_reset_hc()
660 outw(0, base + UHCI_USBCMD); in uhci_reset_hc()
670 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) in uhci_check_and_reset_hc() argument
692 cmd = inw(base + UHCI_USBCMD); in uhci_check_and_reset_hc()
700 intr = inw(base + UHCI_USBINTR); in uhci_check_and_reset_hc()
710 uhci_reset_hc(pdev, base); in uhci_check_and_reset_hc()
726 unsigned long base in quirk_usb_handoff_uhci() local
749 void __iomem *base; quirk_usb_handoff_ohci() local
929 void __iomem *base, *op_reg_base; quirk_usb_disable_ehci() local
1139 void __iomem *base; quirk_usb_handoff_xhci() local
[all...]

Completed in 25 milliseconds

1...<<41424344454647484950>>...686