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/third_party/ffmpeg/libavcodec/mips/
H A Dac3dsp_mips.c209 float src0, src1, src2, src3, src4, src5, src6, src7; in float_to_fixed24_mips() local
H A Dvp9_intra_msa.c49 v16u8 src1, src2; in ff_vert_32x32_msa() local
64 v16u8 src0, src1, src2, src3; in ff_hor_16x16_msa() local
85 v16u8 src0, src1, src2, src3; in ff_hor_32x32_msa() local
363 v16u8 src0, src1, src2, src3; ff_tm_4x4_msa() local
392 v16u8 src0, src1, src2, src3; ff_tm_8x8_msa() local
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/third_party/ffmpeg/libavcodec/
H A Dmagicyuv.c94 static void magicyuv_median_pred16(uint16_t *dst, const uint16_t *src1, in magicyuv_median_pred16() argument
/third_party/ffmpeg/libavfilter/
H A Dvf_deshake.c120 static void find_block_motion(DeshakeContext *deshake, uint8_t *src1, in find_block_motion() argument
235 static void find_motion(DeshakeContext *deshake, uint8_t *src1, uint8_t *src2, in find_motion() argument
436 uint8_t *src1 = (deshake->ref == NULL) ? in->data[0] : deshake->ref->data[0]; in filter_frame() local
/third_party/ffmpeg/libavcodec/ppc/
H A Dvc1dsp_altivec.c140 vector signed short src0, src1, src2, src3, src4, src5, src6, src7; in vc1_inv_trans_8x8_altivec() local
236 vector signed short src0, src1, src2, src3, src4, src5, src6, src7; vc1_inv_trans_8x4_altivec() local
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/third_party/ffmpeg/libavresample/
H A Ddither.c115 int *src1 = src0 + len; in dither_int_to_float_triangular_c() local
/third_party/mesa3d/src/freedreno/afuc/
H A Dafuc.h164 uint32_t src1 : 5; member
180 uint32_t src1 : 5; /* dst (cread) or src (cwrite) register */ member
H A Ddisasm.c369 bool src1 = true; in disasm_instr() local
447 bool src1 = true; in disasm_instr() local
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/third_party/mesa3d/src/compiler/nir/
H A Dnir_builder.c128 nir_build_alu(nir_builder *build, nir_op op, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3) nir_build_alu() argument
159 nir_build_alu2(nir_builder *build, nir_op op, nir_ssa_def *src0, nir_ssa_def *src1) nir_build_alu2() argument
173 nir_build_alu3(nir_builder *build, nir_op op, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) nir_build_alu3() argument
188 nir_build_alu4(nir_builder *build, nir_op op, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3) nir_build_alu4() argument
411 nir_compare_func(nir_builder *b, enum compare_func func, nir_ssa_def *src0, nir_ssa_def *src1) nir_compare_func() argument
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H A Dnir_instr_set.c213 nir_phi_src *src1 = *(nir_phi_src **)data1; in cmp_phi_src() local
329 nir_srcs_equal(nir_src src1, nir_src src2) in nir_srcs_equal() argument
426 nir_alu_srcs_negative_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2, unsigned src1, unsigned src2) nir_alu_srcs_negative_equal() argument
529 nir_alu_srcs_equal(const nir_alu_instr *alu1, const nir_alu_instr *alu2, unsigned src1, unsigned src2) nir_alu_srcs_equal() argument
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H A Dnir_lower_double_ops.c425 lower_mod(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1) in lower_mod() argument
699 nir_ssa_def *src1 = nir_mov_alu(b, alu->src[1], in lower_doubles_instr() local
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qir.c588 qir_inst(enum qop op, struct qreg dst, struct qreg src0, struct qreg src1) in qir_inst() argument
H A Dvc4_nir_lower_blend.c131 vc4_nir_set_packed_chan(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1, in vc4_nir_set_packed_chan() argument
H A Dvc4_qpu.c196 qpu_a_alu2(enum qpu_op_add op, struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) qpu_a_alu2() argument
217 qpu_m_alu2(enum qpu_op_mul op, struct qpu_reg dst, struct qpu_reg src0, struct qpu_reg src1) qpu_m_alu2() argument
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs_builder.h320 emit(enum opcode opcode, const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2) const emit() argument
389 emit_minmax(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod mod) const emit_minmax() argument
661 CMP(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const CMP() argument
686 CMPN(const dst_reg &dst, const src_reg &src0, const src_reg &src1, brw_conditional_mod condition) const CMPN() argument
720 CSEL(const dst_reg &dst, const src_reg &src0, const src_reg &src1, const src_reg &src2, brw_conditional_mod condition) const CSEL() argument
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/third_party/mesa3d/src/gallium/drivers/svga/svgadump/
H A Dsvga_shader.h194 struct sh_srcreg src1; member
209 struct sh_srcreg src1; member
217 struct sh_srcreg src1; member
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_build_util.cpp266 BuildUtil::mkQuadop(uint8_t q, Value *def, uint8_t l, Value *src0, Value *src1) in mkQuadop() argument
80 mkOp2(operation op, DataType ty, Value *dst, Value *src0, Value *src1) mkOp2() argument
94 mkOp3(operation op, DataType ty, Value *dst, Value *src0, Value *src1, Value *src2) mkOp3() argument
225 mkCmp(operation op, CondCode cc, DataType dstTy, Value *dst, DataType srcTy, Value *src0, Value *src1, Value *src2) mkCmp() argument
/third_party/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_state_fs_linear_llvm.c215 LLVMValueRef src1 = lp_build_zero(gallivm, fs_type); in llvm_fragment_body() local
H A Dlp_test_blend.c155 LLVMValueRef src1; in add_blend_test() local
196 compute_blend_ref_term(unsigned rgb_factor, unsigned alpha_factor, const double *factor, const double *src, const double *src1, const double *dst, const double *con, double *term) compute_blend_ref_term() argument
360 compute_blend_ref(const struct pipe_blend_state *blend, const double *src, const double *src1, const double *dst, const double *con, double *res) compute_blend_ref() argument
471 uint8_t *src, *src1, *dst, *con, *res, *ref; test_one() local
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/third_party/node/deps/v8/src/codegen/arm/
H A Dmacro-assembler-arm.h98 void Push(Register src1, Register src2, Condition cond = al) { in Push() argument
108 void Push(Register src1, Register src2, Register src3, Condition cond = al) { in Push() argument
123 void Push(Register src1, Registe argument
144 Push(Register src1, Register src2, Register src3, Register src4, Register src5, Condition cond = al) Push() argument
178 Pop(Register src1, Register src2, Condition cond = al) Pop() argument
189 Pop(Register src1, Register src2, Register src3, Condition cond = al) Pop() argument
205 Pop(Register src1, Register src2, Register src3, Register src4, Condition cond = al) Pop() argument
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/third_party/node/deps/v8/src/codegen/shared-ia32-x64/
H A Dmacro-assembler-shared-ia32-x64.cc80 void SharedTurboAssembler::Movhps(XMMRegister dst, XMMRegister src1, in Movhps() argument
93 void SharedTurboAssembler::Movlps(XMMRegister dst, XMMRegister src1, in Movlps() argument
106 void SharedTurboAssembler::Pblendvb(XMMRegister dst, XMMRegister src1, in Pblendvb() argument
119 Shufps(XMMRegister dst, XMMRegister src1, XMMRegister src2, uint8_t imm8) Shufps() argument
400 I8x16Shl(XMMRegister dst, XMMRegister src1, uint8_t src2, Register tmp1, XMMRegister tmp2) I8x16Shl() argument
422 I8x16Shl(XMMRegister dst, XMMRegister src1, Register src2, Register tmp1, XMMRegister tmp2, XMMRegister tmp3) I8x16Shl() argument
449 I8x16ShrS(XMMRegister dst, XMMRegister src1, uint8_t src2, XMMRegister tmp) I8x16ShrS() argument
463 I8x16ShrS(XMMRegister dst, XMMRegister src1, Register src2, Register tmp1, XMMRegister tmp2, XMMRegister tmp3) I8x16ShrS() argument
484 I8x16ShrU(XMMRegister dst, XMMRegister src1, uint8_t src2, Register tmp1, XMMRegister tmp2) I8x16ShrU() argument
506 I8x16ShrU(XMMRegister dst, XMMRegister src1, Register src2, Register tmp1, XMMRegister tmp2, XMMRegister tmp3) I8x16ShrU() argument
557 I16x8ExtMulLow(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister scratch, bool is_signed) I16x8ExtMulLow() argument
566 I16x8ExtMulHighS(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister scratch) I16x8ExtMulHighS() argument
590 I16x8ExtMulHighU(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister scratch) I16x8ExtMulHighU() argument
689 I16x8Q15MulRSatS(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister scratch) I16x8Q15MulRSatS() argument
751 I32x4ExtMul(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister scratch, bool low, bool is_signed) I32x4ExtMul() argument
856 I64x2GtS(XMMRegister dst, XMMRegister src0, XMMRegister src1, XMMRegister scratch) I64x2GtS() argument
890 I64x2GeS(XMMRegister dst, XMMRegister src0, XMMRegister src1, XMMRegister scratch) I64x2GeS() argument
1038 I64x2ExtMul(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister scratch, bool low, bool is_signed) I64x2ExtMul() argument
1121 S128Select(XMMRegister dst, XMMRegister mask, XMMRegister src1, XMMRegister src2, XMMRegister scratch) S128Select() argument
1281 F32x4Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister src3, XMMRegister tmp) F32x4Qfma() argument
1287 F32x4Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister src3, XMMRegister tmp) F32x4Qfms() argument
1293 F64x2Qfma(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister src3, XMMRegister tmp) F64x2Qfma() argument
1299 F64x2Qfms(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister src3, XMMRegister tmp) F64x2Qfms() argument
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/third_party/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c475 uint32_t src0, src1, src2, flags; in i915_translate_instruction() local
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/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_swizzle.c648 LLVMValueRef src1 = src[1]; in lp_build_transpose_aos() local
H A Dlp_bld_tgsi_aos.c435 LLVMValueRef src0, src1, src2; in lp_emit_instruction_aos() local
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/third_party/mesa3d/src/imagination/vulkan/pds/
H A Dpvr_rogue_pds_disasm.h151 struct pvr_operand *src1; member
174 struct pvr_operand *src1; member
184 struct pvr_operand *src1; member
211 struct pvr_operand *src1; member
220 struct pvr_operand *src1; member
232 struct pvr_operand *src1; member
252 struct pvr_operand *src1; member

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