/third_party/mesa3d/src/compiler/nir/ |
H A D | nir_lower_locals_to_regs.c | 120 nir_register *reg = nir_local_reg_create(state->builder.impl); in get_reg_for_deref() local [all...] |
/third_party/mesa3d/src/compiler/nir/tests/ |
H A D | negative_equal_tests.cpp | 309 nir_register *reg = nir_local_reg_create(bld.impl); in TEST_F() local
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/third_party/mesa3d/src/freedreno/afuc/ |
H A D | emu-regs.c | 245 unsigned reg = get_reg_addr(emu); in emu_set_fifo_reg() local 338 emu_reg_offset(struct emu_reg *reg) in emu_reg_offset() argument 346 emu_get_reg32(struct emu *emu, struct emu_reg *reg) emu_get_reg32() argument 352 emu_get_reg64(struct emu *emu, struct emu_reg *reg) emu_get_reg64() argument 361 emu_set_reg32(struct emu *emu, struct emu_reg *reg, uint32_t val) emu_set_reg32() argument 367 emu_set_reg64(struct emu *emu, struct emu_reg *reg, uint64_t val) emu_set_reg64() argument [all...] |
/third_party/mesa3d/src/asahi/compiler/ |
H A D | agx_register_allocate.c | 115 unsigned reg = ssa_to_reg[I->src[0].value]; in agx_ra_assign_local() local 152 unsigned reg in agx_ra_assign_local() local 167 unsigned reg = agx_assign_regs(used_regs, count, align, AGX_NUM_REGS); agx_ra_assign_local() local [all...] |
/third_party/mesa3d/src/broadcom/compiler/ |
H A D | vir_to_qpu.c | 31 struct qpu_reg reg = { in qpu_reg() local 41 struct qpu_reg reg = { in qpu_magic() local
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H A D | vir_live_variables.c | 40 vir_reg_to_var(struct qreg reg) in vir_reg_to_var() argument
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/third_party/mesa3d/src/amd/vulkan/ |
H A D | radv_cs.h | 43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq() argument 53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() argument 60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq() argument 70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_context_reg() argument 77 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_context_reg_idx() argument 87 radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask) radeon_set_context_reg_rmw() argument 98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_sh_reg_seq() argument 108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_sh_reg() argument 115 radeon_set_sh_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_sh_reg_idx() argument 132 gfx10_set_sh_reg_idx3(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) gfx10_set_sh_reg_idx3() argument 143 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq() argument 153 radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) radeon_set_uconfig_reg_seq_perfctr() argument 163 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_uconfig_reg() argument 170 radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value) radeon_set_uconfig_reg_idx() argument 188 radeon_set_perfctr_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, unsigned value) radeon_set_perfctr_reg() argument 208 radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) radeon_set_privileged_config_reg() argument [all...] |
/third_party/mesa3d/src/intel/compiler/ |
H A D | brw_fs_live_variables.cpp | 118 fs_reg reg = inst->src[i]; in setup_def_use() local 133 fs_reg reg = inst->dst; in setup_def_use() local 56 setup_one_read(struct block_data *bd, int ip, const fs_reg ®) setup_one_read() argument 74 setup_one_write(struct block_data *bd, fs_inst *inst, int ip, const fs_reg ®) setup_one_write() argument 327 check_register_live_range(const fs_live_variables *live, int ip, const fs_reg ®, unsigned n) check_register_live_range() argument [all...] |
H A D | brw_clip.h | 89 } reg; member
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H A D | brw_vec4_copy_propagation.cpp | 502 const unsigned reg = (alloc.offsets[inst->src[i].nr] + in opt_copy_propagation() local 514 const int reg = in opt_copy_propagation() local
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H A D | gfx6_gs_visitor.cpp | 413 dst_reg reg = dst_reg(MRF, mrf); in emit_thread_end() local 501 int reg = 0; in setup_payload() local [all...] |
H A D | brw_vec4_tes.cpp | 51 int reg = 0; in setup_payload() local
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/third_party/mesa3d/src/gallium/drivers/vc4/ |
H A D | vc4_qir_live_variables.c | 38 qir_reg_to_var(struct qreg reg) in qir_reg_to_var() argument
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
H A D | sfn_debug.h | 60 reg = 1 << 6, enumerator
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/third_party/node/deps/base64/base64/test/ |
H A D | benchmark.c | 41 char *reg; member
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/third_party/mesa3d/src/panfrost/bifrost/test/ |
H A D | test-constant-fold.cpp | 102 bi_index reg = bi_register(0); in TEST_F() local 123 bi_index reg = bi_register(0); in TEST_F() local 143 bi_index reg in TEST_F() local 157 bi_index reg = bi_register(0); TEST_F() local 174 bi_index reg = bi_register(0); TEST_F() local 193 bi_index reg = bi_register(0); TEST_F() local 204 bi_index reg = bi_register(0); TEST_F() local [all...] |
/third_party/mesa3d/src/panfrost/midgard/ |
H A D | midgard_print.c | 49 int reg = SSA_REG_FROM_FIXED(source); in mir_print_index() local
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/third_party/mesa3d/src/util/ |
H A D | register_allocate_internal.h | 104 unsigned int reg; member
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/third_party/mesa3d/src/panfrost/lib/ |
H A D | pan_props.c | 254 unsigned reg = panfrost_query_raw(fd, in panfrost_query_afbc() local
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/third_party/node/deps/v8/src/codegen/ |
H A D | interface-descriptors.cc | 24 Register reg = registers[i]; in InitializeRegisters() local 120 bool CallInterfaceDescriptor::IsValidFloatParameterRegister(Register reg) { in IsValidFloatParameterRegister() argument
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H A D | register-configuration.cc | 198 auto reg = Register::from_code(Default()->GetAllocatableGeneralCode(i)); in RestrictGeneralRegisters() local
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/third_party/node/deps/v8/src/interpreter/ |
H A D | bytecode-decoder.cc | 169 Register reg = in Decode() local
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/third_party/mesa3d/src/gallium/drivers/iris/ |
H A D | iris_perf.c | 59 iris_perf_store_register_mem(void *ctx, void *bo, uint32_t reg, uint32_t reg_size, uint32_t offset) iris_perf_store_register_mem() argument
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/third_party/mesa3d/src/gallium/drivers/lima/ir/gp/ |
H A D | reduce_scheduler.c | 71 float reg[n]; in schedule_calc_sched_info() local [all...] |
/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/ |
H A D | liveness.c | 81 ppir_reg *reg = ppir_src_get_reg(src); in ppir_liveness_instr_srcs() local 142 ppir_reg *reg = ppir_dest_get_reg(dest); in ppir_liveness_instr_dest() local [all...] |