Lines Matching defs:reg
43 radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
45 assert(reg >= SI_CONFIG_REG_OFFSET && reg < SI_CONFIG_REG_END);
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
55 radeon_set_config_reg_seq(cs, reg, 1);
60 radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
62 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
66 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
70 radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
72 radeon_set_context_reg_seq(cs, reg, 1);
77 radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, unsigned value)
79 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
82 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
87 radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned mask)
89 assert(reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END);
92 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
100 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
104 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2);
108 radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
110 radeon_set_sh_reg_seq(cs, reg, 1);
116 unsigned reg, unsigned idx, unsigned value)
118 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
127 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (idx << 28));
132 gfx10_set_sh_reg_idx3(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
134 assert(reg >= SI_SH_REG_OFFSET && reg < SI_SH_REG_END);
138 radeon_emit(cs, (reg - SI_SH_REG_OFFSET) >> 2 | (3 << 28));
143 radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
145 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
149 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
153 radeon_set_uconfig_reg_seq_perfctr(struct radeon_cmdbuf *cs, unsigned reg, unsigned num)
155 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
159 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
163 radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
165 radeon_set_uconfig_reg_seq(cs, reg, 1);
171 unsigned reg, unsigned idx, unsigned value)
173 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
183 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2 | (idx << 28));
188 radeon_set_perfctr_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, unsigned value)
191 assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END);
203 radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2);
208 radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value)
210 assert(reg < CIK_UCONFIG_REG_OFFSET);
217 radeon_emit(cs, reg >> 2);