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Searched defs:opcode (Results 651 - 675 of 692) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_shader.c3443 unsigned opcode; in r600_shader_from_tgsi() local
7560 int opcode; in tgsi_tex() local
9375 get_gds_op(int opcode) get_gds_op() argument
9506 get_lds_op(int opcode) get_lds_op() argument
10387 emit_logic_pred(struct r600_shader_ctx *ctx, int opcode, int alu_type, struct r600_bytecode_alu_src *src) emit_logic_pred() argument
10630 emit_if(struct r600_shader_ctx *ctx, int opcode, struct r600_bytecode_alu_src *src) emit_if() argument
[all...]
H A Dr600_isa.h173 int opcode[2]; member
186 int opcode[4]; member
195 int opcode[4]; member
728 r600_isa_alu_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_op3) { in r600_isa_alu_by_opcode() argument
742 r600_isa_fetch_by_opcode(struct r600_isa* isa, unsigned opcode) r600_isa_fetch_by_opcode() argument
751 r600_isa_cf_by_opcode(struct r600_isa* isa, unsigned opcode, unsigned is_alu) r600_isa_cf_by_opcode() argument
[all...]
/third_party/node/deps/v8/src/wasm/baseline/mips/
H A Dliftoff-assembler-mips.h1380 bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, in emit_type_conversion() argument
/third_party/node/deps/v8/src/wasm/baseline/loong64/
H A Dliftoff-assembler-loong64.h1320 bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, in emit_type_conversion() argument
/third_party/mesa3d/src/microsoft/compiler/
H A Ddxil_module.c2631 dxil_emit_binop(struct dxil_module *m, enum dxil_bin_opcode opcode, in dxil_emit_binop() argument
2688 dxil_emit_cast(struct dxil_module *m, enum dxil_cast_opcode opcode, in dxil_emit_cast() argument
H A Dnir_to_dxil.c520 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, intr); in emit_unary_call() local
541 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, intr); in emit_binary_call() local
565 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, intr); in emit_tertiary_call() local
591 const struct dxil_value *opcode in emit_quaternary_call() local
613 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_threadid_call() local
635 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_threadidingroup_call() local
656 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_flattenedthreadidingroup_call() local
676 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_groupid_call() local
699 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_bufferload_call() local
719 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_bufferstore_call() local
743 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_textureload_call() local
766 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, emit_texturestore_call() local
790 const struct dxil_value *opcode = emit_atomic_binop() local
815 const struct dxil_value *opcode = emit_atomic_cmpxchg() local
831 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_CREATE_HANDLE); emit_createhandle_call() local
1824 emit_binop(struct ntd_context *ctx, nir_alu_instr *alu, enum dxil_bin_opcode opcode, const struct dxil_value *op0, const struct dxil_value *op1) emit_binop() argument
1842 emit_shift(struct ntd_context *ctx, nir_alu_instr *alu, enum dxil_bin_opcode opcode, const struct dxil_value *op0, const struct dxil_value *op1) emit_shift() argument
1979 enum dxil_cast_opcode opcode = get_cast_op(alu); emit_cast() local
2209 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_LEGACY_F16TOF32); emit_f16tof32() local
2234 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_LEGACY_F32TOF16); emit_f32tof16() local
2291 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_MAKE_DOUBLE); emit_make_double() local
2317 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_SPLIT_DOUBLE); emit_split_double() local
2518 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_CBUFFER_LOAD_LEGACY); load_ubo() local
2535 const struct dxil_value *opcode, *mode; emit_barrier_impl() local
2710 const struct dxil_value *opcode = call_unary_external_function() local
2758 const struct dxil_value *opcode = emit_load_tess_coord() local
3172 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, is_patch_constant ? emit_store_output_via_intrinsic() local
3282 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, opcode_val); emit_load_input_via_intrinsic() local
3568 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_DISCARD); emit_discard_if_with_value() local
3604 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_EMIT_STREAM); emit_emit_vertex() local
3624 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_CUT_STREAM); emit_end_primitive() local
4163 const struct dxil_value *opcode = dxil_module_get_int32_const(&ctx->mod, DXIL_INTR_RENDER_TARGET_GET_SAMPLE_POSITION); emit_load_sample_pos_from_id() local
4694 enum dxil_intr opcode; emit_sample_cmp() local
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/third_party/node/deps/v8/src/codegen/mips64/
H A Dassembler-mips64.cc442 uint32_t opcode = GetOpcodeField(instr); in IsMsaBranch() local
466 uint32_t opcode = GetOpcodeField(instr); in IsBranch() local
490 uint32_t opcode = GetOpcodeField(instr); IsBc() local
496 uint32_t opcode = GetOpcodeField(instr); IsNal() local
503 uint32_t opcode = GetOpcodeField(instr); IsBzc() local
519 uint32_t opcode = GetOpcodeField(instr); IsBeqzc() local
524 uint32_t opcode = GetOpcodeField(instr); IsBnezc() local
529 uint32_t opcode = GetOpcodeField(instr); IsBeqc() local
536 uint32_t opcode = GetOpcodeField(instr); IsBnec() local
543 uint32_t opcode = GetOpcodeField(instr); IsMov() local
557 uint32_t opcode = GetOpcodeField(instr); IsJump() local
569 uint32_t opcode = GetOpcodeField(instr); IsJ() local
585 uint32_t opcode = GetOpcodeField(instr); IsLui() local
591 uint32_t opcode = GetOpcodeField(instr); IsOri() local
599 uint32_t opcode = GetOpcodeField(instr); IsNop() local
1038 uint32_t opcode = GetOpcodeField(instr); BranchOffset() local
1067 GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, uint16_t sa, SecondaryField func) GenInstrRegister() argument
1076 GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, uint16_t lsb, SecondaryField func) GenInstrRegister() argument
1085 GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, FPURegister fs, FPURegister fd, SecondaryField func) GenInstrRegister() argument
1094 GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft, FPURegister fs, FPURegister fd, SecondaryField func) GenInstrRegister() argument
1103 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPURegister fs, FPURegister fd, SecondaryField func) GenInstrRegister() argument
1112 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPUControlRegister fs, SecondaryField func) GenInstrRegister() argument
1122 GenInstrImmediate(Opcode opcode, Register rs, Register rt, int32_t j, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1131 GenInstrImmediate(Opcode opcode, Register base, Register rt, int32_t offset9, int bit6, SecondaryField func) GenInstrImmediate() argument
1142 GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF, int32_t j, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1150 GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft, int32_t j, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1159 GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1166 GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21) GenInstrImmediate() argument
1173 GenInstrImmediate(Opcode opcode, int32_t offset26, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1180 GenInstrJump(Opcode opcode, uint32_t address) GenInstrJump() argument
[all...]
/third_party/node/deps/v8/src/codegen/mips/
H A Dassembler-mips.cc464 uint32_t opcode = GetOpcodeField(instr); in IsMsaBranch() local
488 uint32_t opcode = GetOpcodeField(instr); in IsBranch() local
512 uint32_t opcode = GetOpcodeField(instr); IsBc() local
518 uint32_t opcode = GetOpcodeField(instr); IsNal() local
525 uint32_t opcode = GetOpcodeField(instr); IsBzc() local
541 uint32_t opcode = GetOpcodeField(instr); IsBeqzc() local
546 uint32_t opcode = GetOpcodeField(instr); IsBnezc() local
551 uint32_t opcode = GetOpcodeField(instr); IsBeqc() local
558 uint32_t opcode = GetOpcodeField(instr); IsBnec() local
565 uint32_t opcode = GetOpcodeField(instr); IsJicOrJialc() local
571 uint32_t opcode = GetOpcodeField(instr); IsJump() local
583 uint32_t opcode = GetOpcodeField(instr); IsJ() local
605 uint32_t opcode = GetOpcodeField(instr); IsLui() local
611 uint32_t opcode = GetOpcodeField(instr); IsOri() local
617 uint32_t opcode = GetOpcodeField(instr); IsAddu() local
631 uint32_t opcode = GetOpcodeField(instr); IsMov() local
647 uint32_t opcode = GetOpcodeField(instr); IsNop() local
1109 uint32_t opcode = GetOpcodeField(instr); BranchOffset() local
1138 GenInstrRegister(Opcode opcode, Register rs, Register rt, Register rd, uint16_t sa, SecondaryField func) GenInstrRegister() argument
1147 GenInstrRegister(Opcode opcode, Register rs, Register rt, uint16_t msb, uint16_t lsb, SecondaryField func) GenInstrRegister() argument
1156 GenInstrRegister(Opcode opcode, SecondaryField fmt, FPURegister ft, FPURegister fs, FPURegister fd, SecondaryField func) GenInstrRegister() argument
1165 GenInstrRegister(Opcode opcode, FPURegister fr, FPURegister ft, FPURegister fs, FPURegister fd, SecondaryField func) GenInstrRegister() argument
1174 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPURegister fs, FPURegister fd, SecondaryField func) GenInstrRegister() argument
1183 GenInstrRegister(Opcode opcode, SecondaryField fmt, Register rt, FPUControlRegister fs, SecondaryField func) GenInstrRegister() argument
1193 GenInstrImmediate(Opcode opcode, Register rs, Register rt, int32_t j, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1202 GenInstrImmediate(Opcode opcode, Register base, Register rt, int32_t offset9, int bit6, SecondaryField func) GenInstrImmediate() argument
1213 GenInstrImmediate(Opcode opcode, Register rs, SecondaryField SF, int32_t j, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1221 GenInstrImmediate(Opcode opcode, Register rs, FPURegister ft, int32_t j, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1230 GenInstrImmediate(Opcode opcode, Register rs, int32_t offset21, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1237 GenInstrImmediate(Opcode opcode, Register rs, uint32_t offset21) GenInstrImmediate() argument
1244 GenInstrImmediate(Opcode opcode, int32_t offset26, CompactBranchType is_compact_branch) GenInstrImmediate() argument
1251 GenInstrJump(Opcode opcode, uint32_t address) GenInstrJump() argument
[all...]
/third_party/node/deps/v8/src/codegen/loong64/
H A Dassembler-loong64.cc308 uint32_t opcode = (instr >> 26) << 26; in IsBranch() local
318 uint32_t opcode = (instr >> 26) << 26; IsB() local
325 uint32_t opcode = (instr >> 26) << 26; IsBz() local
338 uint32_t opcode = (instr >> 26) << 26; IsJ() local
344 uint32_t opcode = (instr >> 25) << 25; IsLu12i_w() local
349 uint32_t opcode = (instr >> 22) << 22; IsOri() local
354 uint32_t opcode = (instr >> 25) << 25; IsLu32i_d() local
359 uint32_t opcode = (instr >> 22) << 22; IsLu52i_d() local
643 uint32_t opcode = (instr >> 26) << 26; BranchOffset() local
678 GenB(Opcode opcode, Register rj, int32_t si21) GenB() argument
686 GenB(Opcode opcode, CFRegister cj, int32_t si21, bool isEq) GenB() argument
696 GenB(Opcode opcode, int32_t si26) GenB() argument
704 GenBJ(Opcode opcode, Register rj, Register rd, int32_t si16) GenBJ() argument
712 GenCmp(Opcode opcode, FPUCondition cond, FPURegister fk, FPURegister fj, CFRegister cd) GenCmp() argument
720 GenSel(Opcode opcode, CFRegister ca, FPURegister fk, FPURegister fj, FPURegister rd) GenSel() argument
728 GenRegister(Opcode opcode, Register rj, Register rd, bool rjrd) GenRegister() argument
736 GenRegister(Opcode opcode, FPURegister fj, FPURegister fd) GenRegister() argument
741 GenRegister(Opcode opcode, Register rj, FPURegister fd) GenRegister() argument
748 GenRegister(Opcode opcode, FPURegister fj, Register rd) GenRegister() argument
755 GenRegister(Opcode opcode, Register rj, FPUControlRegister fd) GenRegister() argument
761 GenRegister(Opcode opcode, FPUControlRegister fj, Register rd) GenRegister() argument
767 GenRegister(Opcode opcode, FPURegister fj, CFRegister cd) GenRegister() argument
773 GenRegister(Opcode opcode, CFRegister cj, FPURegister fd) GenRegister() argument
779 GenRegister(Opcode opcode, Register rj, CFRegister cd) GenRegister() argument
785 GenRegister(Opcode opcode, CFRegister cj, Register rd) GenRegister() argument
791 GenRegister(Opcode opcode, Register rk, Register rj, Register rd) GenRegister() argument
798 GenRegister(Opcode opcode, FPURegister fk, FPURegister fj, FPURegister fd) GenRegister() argument
805 GenRegister(Opcode opcode, FPURegister fa, FPURegister fk, FPURegister fj, FPURegister fd) GenRegister() argument
812 GenRegister(Opcode opcode, Register rk, Register rj, FPURegister fd) GenRegister() argument
819 GenImm(Opcode opcode, int32_t bit3, Register rk, Register rj, Register rd) GenImm() argument
827 GenImm(Opcode opcode, int32_t bit6m, int32_t bit6l, Register rj, Register rd) GenImm() argument
835 GenImm(Opcode opcode, int32_t bit20, Register rd) GenImm() argument
841 GenImm(Opcode opcode, int32_t bit15) GenImm() argument
847 GenImm(Opcode opcode, int32_t value, Register rj, Register rd, int32_t value_bits) GenImm() argument
863 GenImm(Opcode opcode, int32_t bit12, Register rj, FPURegister fd) GenImm() argument
[all...]
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc1224 uint32_t opcode = instr & kOpCodeMask; in AddrMode1() local
[all...]
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dassembler-riscv64.cc817 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, in GenInstrR() argument
827 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, in GenInstrR() argument
837 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, in GenInstrR() argument
847 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, in GenInstrR() argument
857 void Assembler::GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, in GenInstrR() argument
867 GenInstrR(uint8_t funct7, uint8_t funct3, Opcode opcode, Register rd, FPURegister rs1, FPURegister rs2) GenInstrR() argument
877 GenInstrR4(uint8_t funct2, Opcode opcode, Register rd, Register rs1, Register rs2, Register rs3, RoundingMode frm) GenInstrR4() argument
888 GenInstrR4(uint8_t funct2, Opcode opcode, FPURegister rd, FPURegister rs1, FPURegister rs2, FPURegister rs3, RoundingMode frm) GenInstrR4() argument
910 GenInstrRFrm(uint8_t funct7, Opcode opcode, Register rd, Register rs1, Register rs2, RoundingMode frm) GenInstrRFrm() argument
919 GenInstrI(uint8_t funct3, Opcode opcode, Register rd, Register rs1, int16_t imm12) GenInstrI() argument
928 GenInstrI(uint8_t funct3, Opcode opcode, FPURegister rd, Register rs1, int16_t imm12) GenInstrI() argument
937 GenInstrIShift(bool arithshift, uint8_t funct3, Opcode opcode, Register rd, Register rs1, uint8_t shamt) GenInstrIShift() argument
947 GenInstrIShiftW(bool arithshift, uint8_t funct3, Opcode opcode, Register rd, Register rs1, uint8_t shamt) GenInstrIShiftW() argument
957 GenInstrS(uint8_t funct3, Opcode opcode, Register rs1, Register rs2, int16_t imm12) GenInstrS() argument
968 GenInstrS(uint8_t funct3, Opcode opcode, Register rs1, FPURegister rs2, int16_t imm12) GenInstrS() argument
979 GenInstrB(uint8_t funct3, Opcode opcode, Register rs1, Register rs2, int16_t imm13) GenInstrB() argument
992 GenInstrU(Opcode opcode, Register rd, int32_t imm20) GenInstrU() argument
998 GenInstrJ(Opcode opcode, Register rd, int32_t imm21) GenInstrJ() argument
1008 GenInstrCR(uint8_t funct4, Opcode opcode, Register rd, Register rs2) GenInstrCR() argument
1016 GenInstrCA(uint8_t funct6, Opcode opcode, Register rd, uint8_t funct, Register rs2) GenInstrCA() argument
1026 GenInstrCI(uint8_t funct3, Opcode opcode, Register rd, int8_t imm6) GenInstrCI() argument
1035 GenInstrCIU(uint8_t funct3, Opcode opcode, Register rd, uint8_t uimm6) GenInstrCIU() argument
1044 GenInstrCIU(uint8_t funct3, Opcode opcode, FPURegister rd, uint8_t uimm6) GenInstrCIU() argument
1053 GenInstrCIW(uint8_t funct3, Opcode opcode, Register rd, uint8_t uimm8) GenInstrCIW() argument
1062 GenInstrCSS(uint8_t funct3, Opcode opcode, Register rs2, uint8_t uimm6) GenInstrCSS() argument
1070 GenInstrCSS(uint8_t funct3, Opcode opcode, FPURegister rs2, uint8_t uimm6) GenInstrCSS() argument
1078 GenInstrCL(uint8_t funct3, Opcode opcode, Register rd, Register rs1, uint8_t uimm5) GenInstrCL() argument
1089 GenInstrCL(uint8_t funct3, Opcode opcode, FPURegister rd, Register rs1, uint8_t uimm5) GenInstrCL() argument
1099 GenInstrCJ(uint8_t funct3, Opcode opcode, uint16_t uint11) GenInstrCJ() argument
1105 GenInstrCS(uint8_t funct3, Opcode opcode, Register rs2, Register rs1, uint8_t uimm5) GenInstrCS() argument
1116 GenInstrCS(uint8_t funct3, Opcode opcode, FPURegister rs2, Register rs1, uint8_t uimm5) GenInstrCS() argument
1127 GenInstrCB(uint8_t funct3, Opcode opcode, Register rs1, uint8_t uimm8) GenInstrCB() argument
1136 GenInstrCBA(uint8_t funct3, uint8_t funct2, Opcode opcode, Register rs1, int8_t imm6) GenInstrCBA() argument
1146 GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, VRegister vs1, VRegister vs2, MaskType mask) GenInstrV() argument
1156 GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, int8_t vs1, VRegister vs2, MaskType mask) GenInstrV() argument
1166 GenInstrV(uint8_t funct6, Opcode opcode, Register rd, VRegister vs1, VRegister vs2, MaskType mask) GenInstrV() argument
1177 GenInstrV(uint8_t funct6, Opcode opcode, FPURegister fd, VRegister vs1, VRegister vs2, MaskType mask) GenInstrV() argument
1188 GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, Register rs1, VRegister vs2, MaskType mask) GenInstrV() argument
1199 GenInstrV(uint8_t funct6, Opcode opcode, VRegister vd, FPURegister fs1, VRegister vs2, MaskType mask) GenInstrV() argument
1230 GenInstrV(Opcode opcode, uint8_t width, VRegister vd, Register rs1, uint8_t umop, MaskType mask, uint8_t IsMop, bool IsMew, uint8_t Nf) GenInstrV() argument
1244 GenInstrV(Opcode opcode, uint8_t width, VRegister vd, Register rs1, Register rs2, MaskType mask, uint8_t IsMop, bool IsMew, uint8_t Nf) GenInstrV() argument
1259 GenInstrV(Opcode opcode, uint8_t width, VRegister vd, Register rs1, VRegister vs2, MaskType mask, uint8_t IsMop, bool IsMew, uint8_t Nf) GenInstrV() argument
1274 GenInstrV(uint8_t funct6, Opcode opcode, Register rd, uint8_t vs1, VRegister vs2, MaskType mask) GenInstrV() argument
[all...]
/third_party/node/deps/v8/src/wasm/baseline/x64/
H A Dliftoff-assembler-x64.h1991 bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, in emit_type_conversion() argument
/third_party/node/deps/v8/src/wasm/baseline/riscv64/
H A Dliftoff-assembler-riscv64.h1435 bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, in emit_type_conversion() argument
/third_party/node/deps/v8/src/wasm/baseline/mips64/
H A Dliftoff-assembler-mips64.h1464 bool LiftoffAssembler::emit_type_conversion(WasmOpcode opcode, in emit_type_conversion() argument
/third_party/skia/third_party/externals/angle2/src/libGL/
H A Dentry_points_gl_1_autogen.cpp3388 void GL_APIENTRY GL_LogicOp(GLenum opcode) in GL_LogicOp() argument
/third_party/python/Modules/
H A D_pickle.c49 enum opcode { enum
[all...]
/third_party/skia/third_party/externals/tint/src/reader/spirv/
H A Dfunction.cc152 bool GetUnaryOp(SpvOp opcode, ast::UnaryOp* ast_unary_op) { in GetUnaryOp() argument
173 const char* GetUnaryBuiltInFunctionName(SpvOp opcode) { in GetUnaryBuiltInFunctionName() argument
194 ConvertBinaryOp(SpvOp opcode) ConvertBinaryOp() argument
265 NegatedFloatCompare(SpvOp opcode) NegatedFloatCompare() argument
440 GetIntrinsic(SpvOp opcode) GetIntrinsic() argument
475 IsSampledImageAccess(SpvOp opcode) IsSampledImageAccess() argument
498 IsImageSampling(SpvOp opcode) IsImageSampling() argument
519 IsRawImageAccess(SpvOp opcode) IsRawImageAccess() argument
533 IsImageQuery(SpvOp opcode) IsImageQuery() argument
610 auto opcode = terminator->opcode(); VisitBackward() local
3841 const auto opcode = inst.opcode(); MaybeEmitCombinatorialValue() local
4803 const auto opcode = inst.opcode(); FindValuesNeedingNamedOrHoistedDefinition() local
4979 const auto opcode = inst.opcode(); MakeNumericConversion() local
5241 const auto opcode = inst.opcode(); EmitImageAccess() local
5524 const auto opcode = inst.opcode(); EmitImageQuery() local
[all...]
/third_party/toybox/toys/pending/
H A Dawk.c3458 static void gsub(int opcode, int nargs, int parmbase) in gsub() argument
3568 int opcode, op2, k, r, nargs, nsubscrs, range_num, parmbase = 0; in interpx() local
[all...]
/third_party/python/Python/
H A Dceval.c134 int opcode = _Py_OPCODE(*next_instr); in lltrace_instruction() local
1650 uint8_t opcode; /* Current opcode */ global() local
[all...]
/third_party/elfutils/src/
H A Dreadelf.c6407 unsigned int opcode = *readp++; in print_cfa_program() local
8970 unsigned int opcode = *linep++; print_debug_line_section() local
10115 unsigned int opcode = *readp++; print_debug_macinfo_section() local
10352 unsigned int opcode = *readp++; print_debug_macro_section() local
10389 unsigned int opcode = *readp++; print_debug_macro_section() local
[all...]
/third_party/mesa3d/src/glx/tests/
H A Dindirect_api.cpp217 void __indirect_glLogicOp(GLenum opcode) { } in __indirect_glLogicOp() argument
/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_tgsi_vgpu10.c853 translate_opcode(enum tgsi_opcode opcode) in translate_opcode() argument
6487 emit_instruction_opn(struct svga_shader_emitter_v10 *emit, unsigned opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3, boolean saturate, bool precise) emit_instruction_opn() argument
6509 emit_instruction_op1(struct svga_shader_emitter_v10 *emit, unsigned opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src) emit_instruction_op1() argument
6518 emit_instruction_op2(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2) emit_instruction_op2() argument
6528 emit_instruction_op3(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src1, const struct tgsi_full_src_register *src2, const struct tgsi_full_src_register *src3) emit_instruction_op3() argument
6539 emit_instruction_op0(struct svga_shader_emitter_v10 *emit, VGPU10_OPCODE_TYPE opcode) emit_instruction_op0() argument
6978 VGPU10_OPCODE_TYPE opcode; emit_arl_uarl() local
8643 VGPU10_OPCODE_TYPE opcode; emit_tex() local
8871 VGPU10_OPCODE_TYPE opcode; emit_tex2() local
8921 VGPU10_OPCODE_TYPE opcode; emit_txp() local
9080 VGPU10_OPCODE_TYPE opcode; emit_txl_txb() local
9138 unsigned opcode, unit; emit_txl2() local
9213 opcode_has_dbl_dst(unsigned opcode) opcode_has_dbl_dst() argument
9239 opcode_has_dbl_src(unsigned opcode) opcode_has_dbl_src() argument
9649 const enum tgsi_opcode opcode = inst->Instruction.Opcode; emit_simple() local
9771 const enum tgsi_opcode opcode = inst->Instruction.Opcode; emit_bfe() local
9842 const enum tgsi_opcode opcode = inst->Instruction.Opcode; emit_bfi() local
9940 const enum tgsi_opcode opcode = inst->Instruction.Opcode; emit_simple_1dst() local
9973 const enum tgsi_opcode opcode = inst->Instruction.Opcode; emit_vmware() local
10643 VGPU10_OPCODE_TYPE opcode = emit->cur_atomic_opcode; emit_atomic_instruction() local
10703 emit_atomic(struct svga_shader_emitter_v10 *emit, const struct tgsi_full_instruction *inst, VGPU10_OPCODE_TYPE opcode) emit_atomic() argument
10890 const enum tgsi_opcode opcode = inst->Instruction.Opcode; emit_instruction() local
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/third_party/node/deps/v8/src/compiler/
H A Dwasm-compiler.cc841 Binop(wasm::WasmOpcode opcode, Node* left, Node* right, wasm::WasmCodePosition position) Binop() argument
1126 Unop(wasm::WasmOpcode opcode, Node* input, wasm::WasmCodePosition position) Unop() argument
1917 IntConvertType(wasm::WasmOpcode opcode) IntConvertType() argument
1944 FloatConvertType(wasm::WasmOpcode opcode) FloatConvertType() argument
1969 ConvertOp(WasmGraphBuilder* builder, wasm::WasmOpcode opcode) ConvertOp() argument
2006 ConvertBackOp(wasm::WasmOpcode opcode) ConvertBackOp() argument
2025 IsTrappingConvertOp(wasm::WasmOpcode opcode) IsTrappingConvertOp() argument
2128 ConvertTrapTest(WasmGraphBuilder* builder, wasm::WasmOpcode opcode, const MachineType& int_ty, const MachineType& float_ty, Node* trunc, Node* converted_value) ConvertTrapTest() argument
2139 ConvertSaturateTest(WasmGraphBuilder* builder, wasm::WasmOpcode opcode, const MachineType& int_ty, const MachineType& float_ty, Node* trunc, Node* converted_value) ConvertSaturateTest() argument
2153 BuildIntConvertFloat(Node* input, wasm::WasmCodePosition position, wasm::WasmOpcode opcode) BuildIntConvertFloat() argument
2398 convert_ccall_ref(wasm::WasmOpcode opcode) convert_ccall_ref() argument
2419 BuildCcallConvertFloat(Node* input, wasm::WasmCodePosition position, wasm::WasmOpcode opcode) BuildCcallConvertFloat() argument
4442 SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) SimdOp() argument
5093 SimdLaneOp(wasm::WasmOpcode opcode, uint8_t lane, Node* const* inputs) SimdLaneOp() argument
5151 AtomicOp(wasm::WasmOpcode opcode, Node* const* inputs, uint32_t alignment, uint64_t offset, wasm::WasmCodePosition position) AtomicOp() argument
5197 Get(wasm::WasmOpcode opcode) AtomicOp() argument
5404 FATAL_UNSUPPORTED_OPCODE(opcode); AtomicOp() variable
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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_eu_defines.h177 enum opcode { enum
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/third_party/pcre2/pcre2/src/
H A Dpcre2_jit_compile.c9866 PCRE2_UCHAR opcode; in compile_assert_matchingpath() local
10449 PCRE2_UCHAR opcode; compile_bracket_matchingpath() local
11010 PCRE2_UCHAR opcode; compile_bracketpos_matchingpath() local
11289 get_iterator_parameters(compiler_common *common, PCRE2_SPTR cc, PCRE2_UCHAR *opcode, PCRE2_UCHAR *type, sljit_u32 *max, sljit_u32 *exact, PCRE2_SPTR *end) get_iterator_parameters() argument
11438 PCRE2_UCHAR opcode; compile_iterator_matchingpath() local
12025 PCRE2_UCHAR opcode = *cc; compile_control_verb_matchingpath() local
12421 PCRE2_UCHAR opcode; compile_iterator_backtrackingpath() local
12662 int opcode, stacksize, alt_count, alt_max; compile_bracket_backtrackingpath() local
13193 PCRE2_UCHAR opcode = *current->cc; compile_control_verb_backtrackingpath() local
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