Lines Matching defs:opcode
177 enum opcode {
296 * A generic "send" opcode. The first two sources are the message
314 * opcode but instead of taking a single payload blob they expect their
379 * opcode but instead of taking a single payload blob they expect their
387 * of the matching non-LOGICAL opcode.
407 * of the matching non-LOGICAL opcode.
434 * opcode, but instead of taking a single payload blog they expect their
478 * for the BROADCAST pseudo-opcode.
587 * Unlike VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
597 * This opcode doesn't do an implied move from R0 to the first MRF.
604 * This opcode doesn't do an implied move from R0 to the first MRF. This
651 * have any extraneous bits set prior to execution of this opcode (that is,
685 * Note: This opcode uses an implicit MRF register for the ff_sync message
687 * that MRF register to r0. This opcode will also write to this MRF register
909 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */
925 /** Per-opcode immediate argument. Number of dwords, bit size, or atomic op. */
1240 tgl_swsb_decode(const struct intel_device_info *devinfo, const enum opcode opcode,
1246 (opcode == BRW_OPCODE_SEND ||
1247 opcode == BRW_OPCODE_SENDC ||
1248 opcode == BRW_OPCODE_MATH) ?
1969 * write-back to next level. This opcode does nothing for a RO cache.
1974 * the cache as "clean" (M to V state). This opcode does nothing for a RO