| /third_party/mesa3d/src/util/ |
| H A D | fast_idiv_by_const.c | 57 unsigned div_shift = util_logbase2_64(D); in util_compute_fast_udiv_info() local
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| /device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/ |
| H A D | clk-dclk-divider.c | 91 rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_dclk_branch() argument
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| H A D | clk-pvtm.c | 33 u32 div_shift; member
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 21 int div_shift; member
90 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base, spinlock_t *lock) rockchip_clk_register_ddrclk() argument
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| H A D | clk-half-divider.c | 158 rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_halfdiv() argument
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| /kernel/linux/linux-6.6/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 21 int div_shift; member
90 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base, spinlock_t *lock) rockchip_clk_register_ddrclk() argument
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| H A D | clk-half-divider.c | 158 rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_halfdiv() argument
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| /device/soc/rockchip/common/vendor/drivers/clk/ |
| H A D | clk-pvtm.c | 33 u32 div_shift; member
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| H A D | clk-dclk-divider.c | 92 rockchip_clk_register_dclk_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, unsigned long max_prate, spinlock_t *lock) rockchip_clk_register_dclk_branch() argument
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| /device/soc/rockchip/common/sdk_linux/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 58 u8 div_shift; member
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| /device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 32 int div_shift; member
218 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base) rockchip_clk_register_ddrclk() argument
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| H A D | clk-half-divider.c | 148 rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_halfdiv() argument
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| H A D | clk.c | 37 rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) rockchip_clk_register_branch() argument
371 rockchip_clk_register_composite_brother_branch( struct rockchip_clk_provider *ctx, const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, struct rockchip_clk_branch *brother, spinlock_t *lock) rockchip_clk_register_composite_brother_branch() argument
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/gpu/drm/rockchip/ |
| H A D | rockchip_vop2_clk.c | 69 u8 div_shift; member
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| /kernel/linux/linux-5.10/drivers/clk/at91/ |
| H A D | pmc.h | 63 u8 div_shift; member
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| /kernel/linux/linux-6.6/drivers/clk/at91/ |
| H A D | pmc.h | 65 u8 div_shift; member
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| /kernel/linux/linux-6.6/drivers/clk/ |
| H A D | clk-en7523.c | 40 u8 div_shift; member
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 190 unsigned char div_shift; member
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| /kernel/linux/linux-6.6/sound/soc/fsl/ |
| H A D | fsl_mqs.c | 57 int div_shift; member
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| /kernel/linux/linux-5.10/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 184 unsigned char div_shift; member
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| /kernel/linux/linux-5.10/drivers/clk/x86/ |
| H A D | clk-cgu.h | 182 u8 div_shift; member
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 52 u32 div_shift; member
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| /kernel/linux/linux-6.6/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 53 u32 div_shift; member
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| /kernel/linux/linux-6.6/drivers/clk/x86/ |
| H A D | clk-cgu.h | 182 u8 div_shift; member
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| H A D | clk-s3c2410-dclk.c | 173 s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk, int div_shift, int cmp_shift) s3c24xx_dclk_update_cmp() argument
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