Searched refs:zreg_lane (Results 1 - 3 of 3) sorted by relevance
| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.h | 164 inline T zreg_lane(unsigned code, int lane) const { in zreg_lane() function in vixl::aarch64::RegisterDump
171 inline uint64_t zreg_lane(unsigned code,
176 return zreg_lane<uint8_t>(code, lane);
178 return zreg_lane<uint16_t>(code, lane);
180 return zreg_lane<uint32_t>(code, lane);
182 return zreg_lane<uint64_t>(code, lane);
223 return zreg_lane(reg.GetCode(), reg.GetLaneSizeInBits(), lane); in GetSVELane()
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| H A D | test-assembler-sve-aarch64.cc | 5654 core.zreg_lane(z5.GetCode(), kBRegSize, lane_count - i - 1);
5655 uint64_t input = core.zreg_lane(z9.GetCode(), kBRegSize, i);
5662 core.zreg_lane(z6.GetCode(), kHRegSize, lane_count - i - 1);
5663 uint64_t input = core.zreg_lane(z9.GetCode(), kHRegSize, i);
5670 core.zreg_lane(z7.GetCode(), kSRegSize, lane_count - i - 1);
5671 uint64_t input = core.zreg_lane(z9.GetCode(), kSRegSize, i);
5678 core.zreg_lane(z8.GetCode(), kDRegSize, lane_count - i - 1);
5679 uint64_t input = core.zreg_lane(z9.GetCode(), kDRegSize, i);
5776 uint16_t expected = core.zreg_lane<uint16_t>(z10.GetCode(), i);
5777 uint8_t b_lane = core.zreg_lane<uint8_
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| H A D | test-utils-aarch64.cc | 371 uint64_t result = core->zreg_lane(reg.GetCode(), lane_size, lane); in EqualSVELane()
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