/third_party/ffmpeg/libavutil/ |
H A D | mathematics.c | 38 int za, zb, k; in av_gcd() local 45 zb = ff_ctzll(b); in av_gcd() 46 k = FFMIN(za, zb); in av_gcd() 48 v = llabs(b >> zb); in av_gcd()
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/third_party/vk-gl-cts/framework/referencerenderer/ |
H A D | rrRasterizer.cpp | 548 const float zb = m_v1.z()-m_v2.z(); in rasterizeSingleSample() local 617 depthValues[packetNdx*4+0] = z0[0]*za + z1[0]*zb + zc; in rasterizeSingleSample() 618 depthValues[packetNdx*4+1] = z0[1]*za + z1[1]*zb + zc; in rasterizeSingleSample() 619 depthValues[packetNdx*4+2] = z0[2]*za + z1[2]*zb + zc; in rasterizeSingleSample() 620 depthValues[packetNdx*4+3] = z0[3]*za + z1[3]*zb + zc; in rasterizeSingleSample() 706 const float zb = m_v1.z()-m_v2.z(); 799 depthValues[(packetNdx*4+0)*NumSamples + sampleNdx] = z0[0]*za + z1[0]*zb + zc; 800 depthValues[(packetNdx*4+1)*NumSamples + sampleNdx] = z0[1]*za + z1[1]*zb + zc; 801 depthValues[(packetNdx*4+2)*NumSamples + sampleNdx] = z0[2]*za + z1[2]*zb + zc; 802 depthValues[(packetNdx*4+3)*NumSamples + sampleNdx] = z0[3]*za + z1[3]*zb [all...] |
/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_state.c | 3463 struct si_surface *zb = (struct si_surface *)state->zsbuf; in si_emit_framebuffer_state() local 3464 struct si_texture *tex = (struct si_texture *)zb->base.texture; in si_emit_framebuffer_state() 3465 unsigned db_z_info = zb->db_z_info; in si_emit_framebuffer_state() 3466 unsigned db_stencil_info = zb->db_stencil_info; in si_emit_framebuffer_state() 3467 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() 3470 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA in si_emit_framebuffer_state() 3472 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS); in si_emit_framebuffer_state() 3501 unsigned level = zb->base.u.tex.level; in si_emit_framebuffer_state() 3504 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); in si_emit_framebuffer_state() 3505 radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, zb in si_emit_framebuffer_state() [all...] |
/third_party/libwebsockets/lib/core-net/ |
H A D | network.c | 818 char c, elided = 0, soe = 0, zb = (char)-1, n, ipv4 = 0; in lws_write_numeric_address() local 844 zb = c; in lws_write_numeric_address() 864 if (c == 5 && v == 0xffff && !zb) { in lws_write_numeric_address()
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/third_party/mesa3d/src/amd/common/ |
H A D | ac_surface_meta_address_test.c | 83 unsigned zb = z >> meta_block_depth_log2; in gfx9_meta_addr_from_coord() local 85 unsigned blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb; in gfx9_meta_addr_from_coord()
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H A D | ac_surface.c | 3203 nir_ssa_def *zb = nir_ushr_imm(b, z, meta_block_depth_log2); in gfx9_nir_meta_addr_from_coord() local 3205 nir_ssa_def *blockIndex = nir_iadd(b, nir_iadd(b, nir_imul(b, zb, sliceSizeInBlock), in gfx9_nir_meta_addr_from_coord()
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/third_party/mesa3d/src/amd/addrlib/src/gfx9/ |
H A D | gfx9addrlib.cpp | 886 UINT_32 zb = pIn->slice; in HwlComputeCmaskAddrFromCoord() local 890 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb; in HwlComputeCmaskAddrFromCoord() 963 UINT_32 zb = pIn->slice; in HwlComputeHtileAddrFromCoord() local 967 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb; in HwlComputeHtileAddrFromCoord() 1127 UINT_32 zb = pIn->slice / pIn->metaBlkDepth; in HwlComputeDccAddrFromCoord() local 1131 UINT_32 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb; in HwlComputeDccAddrFromCoord() 5091 UINT_32 zb = pIn->slice / localOut.blockSlices + + mipStartPos.d; 5096 UINT_64 blockIndex = zb * sliceSizeInBlock + yb * pitchInBlock + xb;
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/third_party/mesa3d/src/gallium/drivers/r600/ |
H A D | evergreen_state.c | 1919 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; in evergreen_emit_framebuffer_state() local 1924 (zb->base.texture->nr_samples > 1 ? in evergreen_emit_framebuffer_state() 1928 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); in evergreen_emit_framebuffer_state() 1931 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */ in evergreen_emit_framebuffer_state() 1932 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ in evergreen_emit_framebuffer_state() 1933 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ in evergreen_emit_framebuffer_state() 1934 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ in evergreen_emit_framebuffer_state() 1935 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ in evergreen_emit_framebuffer_state() 1936 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ in evergreen_emit_framebuffer_state() 1937 radeon_emit(cs, zb in evergreen_emit_framebuffer_state() [all...] |
/third_party/libphonenumber/javascript/i18n/phonenumbers/ |
H A D | demo-compiled.js | 495 zb=/\$NP/,Ab=/\$FG/,Bb=/\$CC/,Cb=/^\(?\$1\)?$/;function Db(a){return 2>a.length?!1:K(xb,a)}function Eb(a){return K(sb,a)?L(a,kb):L(a,ib)}function Fb(a){var b=Eb(a.toString());A(a);a.g(b)}function Gb(a){return null!=a&&(1!=w(a,9)||-1!=u(a,9)[0])}function L(a,b){for(var c=new z,d,f=a.length,e=0;e<f;++e)d=a.charAt(e),d=b[d.toUpperCase()],null!=d&&c.g(d);return c.toString()}function Hb(a){return 0==a.length||Cb.test(a)}function Ib(a){return null!=a&&isNaN(a)&&a.toUpperCase()in gb} 682 Ca=v(Va,4);if(0<Ca.length){var jc=v(hc,12);0<jc.length?(Ca=Ca.replace(zb,jc).replace(Ab,"$1"),t(Wa,4,Ca)):Qa(Wa,4)}ic=Rb(Ba,Wa,2)}var id=Kb(e,hc,2);B=Jb(Aa,2,ic,id)}else B=Ba}}}}}var Xa=v(e,5);if(null!=B&&0<Xa.length){var jd=L(B,jb),kd=L(Xa,jb);jd!=kd&&(B=Xa)}ja=B}else ja=M(r,e,2);X.call(d,ja);d.g("\nNational format: ");d.g(M(S,e,2));d.g("\nInternational format: ");d.g(p?M(S,e,1):"invalid");d.g("\nOut-of-country format from US: ");d.g(p?Ob(S,e,"US"):"invalid");d.g("\nOut-of-country format from Switzerland: ");
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/third_party/vixl/src/aarch64/ |
H A D | macro-assembler-aarch64.h | 2360 void MASM_PRE##zb(const Register& xd) { \ 2363 ASM_PRE##zb(xd); \
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H A D | assembler-aarch64.cc | 1067 void Assembler::PRE##zb(const Register& xd) { \
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