Lines Matching refs:zb
3463 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3464 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3465 unsigned db_z_info = zb->db_z_info;
3466 unsigned db_stencil_info = zb->db_stencil_info;
3467 unsigned db_htile_surface = zb->db_htile_surface;
3470 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3472 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS);
3501 unsigned level = zb->base.u.tex.level;
3504 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3505 radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3516 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3517 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3518 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3519 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3522 radeon_emit(zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3523 radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3524 radeon_emit(zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3525 radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3526 radeon_emit(zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3529 radeon_emit(zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3530 radeon_emit(S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3531 radeon_emit(zb->db_depth_size); /* DB_DEPTH_SIZE */
3537 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3538 radeon_emit(S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3539 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3540 radeon_emit(S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3541 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3542 radeon_emit(S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3543 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3544 radeon_emit(S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3547 radeon_emit(zb->db_z_info2); /* DB_Z_INFO2 */
3548 radeon_emit(zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3552 if (si_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3566 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3569 radeon_emit(zb->db_depth_info | /* DB_DEPTH_INFO */
3574 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3575 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3576 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3577 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3578 radeon_emit(zb->db_depth_size); /* DB_DEPTH_SIZE */
3579 radeon_emit(zb->db_depth_slice); /* DB_DEPTH_SLICE */
3586 radeon_set_context_reg(R_028008_DB_DEPTH_VIEW, zb->db_depth_view);