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Searched refs:writemask (Results 1 - 25 of 146) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_cmod_propagation.cpp42 return (earlier->dst.writemask != WRITEMASK_X && in writemasks_incompatible()
43 earlier->dst.writemask != WRITEMASK_XYZW) || in writemasks_incompatible()
44 (earlier->dst.writemask == WRITEMASK_XYZW && in writemasks_incompatible()
46 (later->dst.writemask & ~earlier->dst.writemask) != 0; in writemasks_incompatible()
164 scan_inst->dst.writemask == WRITEMASK_X) || in opt_cmod_propagation_local()
166 scan_inst->dst.writemask == WRITEMASK_Y) || in opt_cmod_propagation_local()
168 scan_inst->dst.writemask == WRITEMASK_Z) || in opt_cmod_propagation_local()
170 scan_inst->dst.writemask == WRITEMASK_W))) { in opt_cmod_propagation_local()
171 if (inst->dst.writemask ! in opt_cmod_propagation_local()
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H A Dbrw_vec4_dead_code_eliminate.cpp87 uint8_t flag_mask = inst->dst.writemask; in dead_code_eliminate()
88 uint8_t dest_mask = inst->dst.writemask; in dead_code_eliminate()
98 if (inst->dst.writemask != (flag_mask | dest_mask)) { in dead_code_eliminate()
100 inst->dst.writemask = flag_mask | dest_mask; in dead_code_eliminate()
112 if (!result_live[c] && inst->dst.writemask & (1 << c)) { in dead_code_eliminate()
113 inst->dst.writemask &= ~(1 << c); in dead_code_eliminate()
116 if (inst->dst.writemask == 0) { in dead_code_eliminate()
144 if (inst->dst.writemask & (1 << c)) { in dead_code_eliminate()
H A Dbrw_vec4.cpp80 this->swizzle = brw_swizzle_for_mask(reg.writemask); in src_reg()
89 this->writemask = WRITEMASK_XYZW; in init()
106 unsigned writemask) in dst_reg()
113 this->writemask = writemask; in dst_reg()
117 unsigned writemask) in dst_reg()
124 this->writemask = writemask; in dst_reg()
137 this->writemask = brw_mask_for_swizzle(reg.swizzle); in dst_reg()
406 unsigned writemask in opt_vector_float() local
105 dst_reg(enum brw_reg_file file, int nr, const glsl_type *type, unsigned writemask) dst_reg() argument
116 dst_reg(enum brw_reg_file file, int nr, brw_reg_type type, unsigned writemask) dst_reg() argument
2054 scalarize_predicate(brw_predicate predicate, unsigned writemask) scalarize_predicate() argument
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H A Dtest_vec4_register_coalesce.cpp145 m0.writemask = WRITEMASK_X; in TEST_F()
164 m0.writemask = WRITEMASK_X; in TEST_F()
168 m1.writemask = WRITEMASK_XYZW; in TEST_F()
190 m0.writemask = WRITEMASK_Y; in TEST_F()
201 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y); in TEST_F()
214 to.writemask = WRITEMASK_Y; in TEST_F()
227 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y); in TEST_F()
240 to.writemask = WRITEMASK_Y; in TEST_F()
H A Dbrw_vec4_visitor.cpp342 if (devinfo->ver == 6 && dst.writemask != WRITEMASK_XYZW) { in emit_math()
415 tmp_dst.writemask = WRITEMASK_XY; in emit_pack_half_2x16()
460 tmp_dst.writemask = WRITEMASK_X; in emit_unpack_half_2x16()
463 tmp_dst.writemask = WRITEMASK_Y; in emit_unpack_half_2x16()
466 dst.writemask = WRITEMASK_XY; in emit_unpack_half_2x16()
710 this->writemask = WRITEMASK_XYZW; in dst_reg()
712 this->writemask = (1 << type->vector_elements) - 1; in dst_reg()
819 ndc_w.writemask = WRITEMASK_W; in emit_ndc_computation()
825 ndc_xyz.writemask = WRITEMASK_XYZ; in emit_ndc_computation()
839 header1_w.writemask in emit_psiz_and_flags()
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H A Dbrw_vec4_surface_builder.cpp45 bld.MOV(writemask(offset(dst, 8, i * dst_stride / 4), in emit_stride()
72 bld.MOV(writemask(tmp, mask), src); in emit_insert()
74 bld.MOV(writemask(tmp, ~mask), brw_imm_d(0)); in emit_insert()
196 bld.MOV(writemask(srcs, WRITEMASK_X), in emit_untyped_atomic()
201 bld.MOV(writemask(srcs, WRITEMASK_Y), in emit_untyped_atomic()
H A Dbrw_vec4_nir.cpp319 ubld.MOV(writemask(offset(tmp, 8, n), WRITEMASK_X), brw_imm_ud(di.i1)); in setup_imm_df()
320 ubld.MOV(writemask(offset(tmp, 8, n), WRITEMASK_Y), brw_imm_ud(di.i2)); in setup_imm_df()
347 unsigned writemask = 1 << i; in nir_emit_load_const() local
349 if ((remaining & writemask) == 0) in nir_emit_load_const()
357 writemask |= 1 << j; in nir_emit_load_const()
361 reg.writemask = writemask; in nir_emit_load_const()
368 remaining &= ~writemask; in nir_emit_load_const()
371 /* Set final writemask */ in nir_emit_load_const()
372 reg.writemask in nir_emit_load_const()
445 int writemask = WRITEMASK_X; nir_emit_intrinsic() local
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H A Dbrw_vec4_cse.cpp113 /* Smash out the values that are not part of the writemask. Otherwise in operands_match()
116 const unsigned ab_writemask = a->dst.writemask & b->dst.writemask; in operands_match()
157 ((a->dst.writemask & b->dst.writemask) == a->dst.writemask) && in instructions_match()
H A Dbrw_vec4_tcs.cpp198 brw_imm_ud(dst.writemask << first_component), indirect_offset); in emit_output_urb_read()
207 /* Read into a temporary and copy with a swizzle and writemask. */ in emit_output_urb_read()
216 unsigned writemask, in emit_urb_write()
220 if (writemask == 0) in emit_urb_write()
227 brw_imm_ud(writemask), indirect_offset); in emit_urb_write()
265 dst.writemask = brw_writemask_for_size(instr->num_components); in nir_emit_intrinsic()
279 dst.writemask = brw_writemask_for_size(instr->num_components); in nir_emit_intrinsic()
215 emit_urb_write(const src_reg &value, unsigned writemask, unsigned base_offset, const src_reg &indirect_offset) emit_urb_write() argument
H A Dtest_vec4_cmod_propagation.cpp163 dest_null.writemask = WRITEMASK_X; in TEST_F()
427 dest_null.writemask = WRITEMASK_X; in TEST_F()
470 dest_null.writemask = WRITEMASK_X; in TEST_F()
502 dest_null.writemask = WRITEMASK_X; in TEST_F()
641 dest.writemask = WRITEMASK_X; in TEST_F()
678 dest.writemask = WRITEMASK_X; in TEST_F()
688 dest_null.writemask = WRITEMASK_X; in TEST_F()
720 dest.writemask = WRITEMASK_XW; in TEST_F()
763 dest.writemask = WRITEMASK_X; in TEST_F()
771 dest_null.writemask in TEST_F()
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/third_party/mesa3d/src/compiler/glsl/
H A Dgl_nir_lower_packed_varyings.c398 unsigned writemask) in bitwise_assign_pack()
430 unsigned writemask = 0x3; in bitwise_assign_pack() local
439 store_state->writemasks[0] = writemask; in bitwise_assign_pack()
442 writemask = 0xc; in bitwise_assign_pack()
450 store_state->writemasks[1] = writemask; in bitwise_assign_pack()
471 store_state->writemasks[0] = writemask; in bitwise_assign_pack()
484 nir_ssa_def *value, unsigned writemask) in bitwise_assign_unpack()
517 writemask = 1 << (ffs(writemask) - 1); in bitwise_assign_unpack()
526 store_state->writemasks[0] = writemask; in bitwise_assign_unpack()
393 bitwise_assign_pack(struct lower_packed_varyings_state *state, nir_deref_instr *packed_deref, nir_deref_instr *unpacked_deref, const struct glsl_type *unpacked_type, nir_ssa_def *value, unsigned writemask) bitwise_assign_pack() argument
480 bitwise_assign_unpack(struct lower_packed_varyings_state *state, nir_deref_instr *unpacked_deref, nir_deref_instr *packed_deref, const struct glsl_type *unpacked_type, nir_ssa_def *value, unsigned writemask) bitwise_assign_unpack() argument
565 create_store_deref(struct lower_packed_varyings_state *state, nir_deref_instr *deref, nir_ssa_def *value, unsigned writemask, bool is_64bit) create_store_deref() argument
618 lower_arraylike(struct lower_packed_varyings_state *state, nir_ssa_def *rhs_swizzle, unsigned writemask, const struct glsl_type *type, unsigned fine_location, nir_variable *unpacked_var, nir_deref_instr *unpacked_var_deref, const char *name, bool gs_input_toplevel, unsigned vertex_index) lower_arraylike() argument
682 lower_varying(struct lower_packed_varyings_state *state, nir_ssa_def *rhs_swizzle, unsigned writemask, const struct glsl_type *type, unsigned fine_location, nir_variable *unpacked_var, nir_deref_instr *unpacked_var_deref, const char *name, bool gs_input_toplevel, unsigned vertex_index) lower_varying() argument
852 unsigned writemask = ((1 << components) - 1) << location_frac; lower_varying() local
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/third_party/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_pair_regalloc.c289 unsigned int writemask, in find_class()
299 if (classes[i].Writemasks[j] == writemask) { in find_class()
332 unsigned int writemask = rc_variable_writemask_sum(variable); in variable_get_class() local
344 writemask = RC_MASK_XYZW; in variable_get_class()
350 class_index = find_class(classes, writemask, 3); in variable_get_class()
365 writemask, c.Writemasks[i]); in variable_get_class()
372 * then the writemask will be set to RC_MASK_XYZW in variable_get_class()
435 class_index = find_class(classes, writemask, in variable_get_class()
444 variable->Dst.Index, writemask); in variable_get_class()
474 static int get_reg_id(unsigned int index, unsigned int writemask) in get_reg_id() argument
287 find_class( const struct rc_class * classes, unsigned int writemask, unsigned int max_writemask_count) find_class() argument
560 unsigned int chan, writemask = 0; do_advanced_regalloc() local
628 unsigned int writemask = reg_get_writemask(reg); do_advanced_regalloc() local
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H A Dradeon_rename_regs.c74 unsigned writemask; in rc_rename_regs() local
88 writemask = rc_variable_writemask_sum(var); in rc_rename_regs()
89 rc_variable_change_dst(var, new_index, writemask); in rc_rename_regs()
H A Dradeon_variable.c40 * Rewrite the index and writemask for the destination register of var
302 unsigned int writemask; in get_variable_pair_helper() local
316 writemask = sub_inst->WriteMask; in get_variable_pair_helper()
319 writemask = sub_inst->OutputWriteMask; in get_variable_pair_helper()
321 writemask = 0; in get_variable_pair_helper()
324 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask, in get_variable_pair_helper()
454 unsigned int writemask = 0; in rc_variable_writemask_sum() local
456 writemask |= var->Dst.WriteMask; in rc_variable_writemask_sum()
459 return writemask; in rc_variable_writemask_sum()
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_instr_export.cpp36 static char *writemask_to_swizzle(int writemask, char *buf) in writemask_to_swizzle() argument
40 buf[i] = (writemask & (1 << i)) ? swz[i] : '_'; in writemask_to_swizzle()
151 int align, int align_offset, int writemask, in ScratchIOInstr()
157 m_writemask(writemask), in ScratchIOInstr()
169 int align, int align_offset,int writemask, in ScratchIOInstr()
175 m_writemask(writemask), in ScratchIOInstr()
265 int writemask = 0; variable
268 writemask |= 1 << i;
288 return new ScratchIOInstr(value, addr_reg->as_register(), align, align_offset, writemask, array_size);
291 return new ScratchIOInstr(value, offset, align, align_offset, writemask);
150 ScratchIOInstr(const RegisterVec4& value, PRegister addr, int align, int align_offset, int writemask, int array_size, bool is_read) ScratchIOInstr() argument
168 ScratchIOInstr(const RegisterVec4& value, int loc, int align, int align_offset,int writemask, bool is_read) ScratchIOInstr() argument
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/third_party/mesa3d/src/gallium/drivers/svga/
H A Dsvga_pipe_depthstencil.c142 /* SVGA3D has one ref/mask/writemask triple shared between front & in svga_create_depth_stencil_state()
146 ds->stencil_writemask = templ->stencil[0].writemask & 0xff; in svga_create_depth_stencil_state()
165 ds->stencil_writemask = templ->stencil[1].writemask & 0xff; in svga_create_depth_stencil_state()
174 if (templ->stencil[1].writemask != templ->stencil[0].writemask) { in svga_create_depth_stencil_state()
176 "two-sided stencil writemask not supported " in svga_create_depth_stencil_state()
178 templ->stencil[0].writemask, in svga_create_depth_stencil_state()
179 templ->stencil[1].writemask); in svga_create_depth_stencil_state()
H A Dsvga_tgsi_insn.c1185 writemask(temp, channel), in emit_div()
1265 if (!do_emit_sincos(emit, writemask(temp, TGSI_WRITEMASK_Y), src0)) in emit_sin()
1293 if (!do_emit_sincos( emit, writemask(temp, TGSI_WRITEMASK_X), src0 )) in emit_cos()
1331 writemask( temp0, dst.mask ), src0, one, zero )) in emit_ssg()
1336 writemask( temp1, dst.mask ), negate( src0 ), negate( one ), in emit_ssg()
1668 writemask( tmp, TGSI_WRITEMASK_W ), in emit_tex2()
1765 writemask(dst, srcWritemask), in emit_tex_swizzle()
1778 writemask(dst, zeroWritemask), in emit_tex_swizzle()
1787 writemask(dst, oneWritemask), in emit_tex_swizzle()
1870 writemask(src0_zdiv in emit_tex()
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/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_zsa.c157 update_lrz_stencil(so, s->func, !!s->writemask); in fd6_zsa_state_create()
168 so->rb_stencilwrmask = A6XX_RB_STENCILWRMASK_WRMASK(s->writemask); in fd6_zsa_state_create()
173 update_lrz_stencil(so, bs->func, !!bs->writemask); in fd6_zsa_state_create()
183 so->rb_stencilwrmask |= A6XX_RB_STENCILWRMASK_BFWRMASK(bs->writemask); in fd6_zsa_state_create()
/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_scan.c995 arrays[dst->Indirect.ArrayID - 1].writemask |= dst->Register.WriteMask; in tgsi_scan_arrays()
999 arrays[j].writemask |= dst->Register.WriteMask; in tgsi_scan_arrays()
1008 array->writemask |= dst->Register.WriteMask; in tgsi_scan_arrays()
1034 unsigned writemask = 0; in get_inst_tessfactor_writemask() local
1044 writemask |= dst->Register.WriteMask; in get_inst_tessfactor_writemask()
1046 writemask |= dst->Register.WriteMask << 4; in get_inst_tessfactor_writemask()
1049 return writemask; in get_inst_tessfactor_writemask()
1058 unsigned writemask = 0; in get_block_tessfactor_writemask() local
1071 writemask |= in get_block_tessfactor_writemask()
1076 writemask | in get_block_tessfactor_writemask()
1106 unsigned writemask; get_if_block_tessfactor_writemask() local
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/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_zsa.c63 if(so->stencil[i].writemask == 0) in etna_zsa_state_create()
121 VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(stencil_front->writemask); in etna_zsa_state_create()
124 VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(stencil_back->writemask); in etna_zsa_state_create()
/third_party/mesa3d/src/compiler/nir/
H A Dnir_opt_large_constants.c106 unsigned writemask, in handle_constant_store()
127 if (!(writemask & (1 << i))) in handle_constant_store()
221 unsigned writemask = 0; in nir_opt_large_constants() local
226 writemask = nir_intrinsic_write_mask(intrin); in nir_opt_large_constants()
264 handle_constant_store(var_infos, info, dst_deref, val, writemask, in nir_opt_large_constants()
104 handle_constant_store(void *mem_ctx, struct var_info *info, nir_deref_instr *deref, nir_const_value *val, unsigned writemask, glsl_type_size_align_func size_align) handle_constant_store() argument
H A Dnir_lower_fragcolor.c81 nir_component_mask_t writemask = nir_intrinsic_write_mask(instr); in lower_fragcolor_instr() local
93 nir_store_var(b, out_color, frag_color, writemask); in lower_fragcolor_instr()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_nir.h98 unsigned writemask,
117 unsigned writemask, unsigned nc, unsigned bit_size,
155 unsigned writemask,
169 unsigned writemask,
179 unsigned writemask, unsigned nc,
/third_party/mesa3d/src/gallium/frontends/d3d10umd/
H A DShaderTGSI.c221 uint writemask; member
401 swizzle_reg(struct ureg_src src, uint writemask, in swizzle_reg() argument
414 &writemask_to_swizzle[writemask]; in swizzle_reg()
427 unsigned writemask = in dcl_base_output() local
432 if (!writemask) { in dcl_base_output()
442 if ((writemask & mask)) { in dcl_base_output()
456 unsigned writemask = in dcl_base_input() local
463 ureg_writemask(temp, sx->inputs[index].writemask), in dcl_base_input()
464 swizzle_reg(sx->inputs[index].reg, sx->inputs[index].writemask, in dcl_base_input()
466 ureg_MOV(ureg, ureg_writemask(temp, writemask), in dcl_base_input()
707 translate_operand(struct Shader_xlate *sx, const struct Shader_operand *operand, unsigned writemask) translate_operand() argument
821 unsigned writemask = translate_dst_operand() local
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/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_zsa.c70 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) | in fd4_zsa_state_create()
84 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) | in fd4_zsa_state_create()

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