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Searched refs:write_enable (Results 1 - 13 of 13) sorted by relevance

/third_party/mesa3d/src/intel/vulkan/
H A Dgfx8_cmd_buffer.c194 return (pipeline->kill_pixel && (ds->depth.write_enable || in want_depth_pma_fix()
195 ds->stencil.write_enable)) || in want_depth_pma_fix()
294 const bool stc_write_en = ds->stencil.write_enable; in want_stencil_pma_fix()
448 ds.DepthBufferWriteEnable = opt_ds.depth.write_enable; in cmd_buffer_flush_dynamic_state()
451 ds.StencilBufferWriteEnable = opt_ds.stencil.write_enable; in cmd_buffer_flush_dynamic_state()
517 ds.DepthBufferWriteEnable = opt_ds.depth.write_enable; in cmd_buffer_flush_dynamic_state()
520 ds.StencilBufferWriteEnable = opt_ds.stencil.write_enable; in cmd_buffer_flush_dynamic_state()
H A Dgfx7_cmd_buffer.c167 .DepthBufferWriteEnable = opt_ds.depth.write_enable, in cmd_buffer_flush_dynamic_state()
170 .StencilBufferWriteEnable = opt_ds.stencil.write_enable, in cmd_buffer_flush_dynamic_state()
/third_party/mesa3d/src/vulkan/runtime/
H A Dvk_graphics_state.h355 bool write_enable; member
393 bool write_enable; member
H A Dvk_graphics_state.c680 ds->depth.write_enable = ds_info->depthWriteEnable; in vk_depth_stencil_state_init()
687 ds->stencil.write_enable = true; in vk_depth_stencil_state_init()
745 /* stencil.write_enable is a dummy right now that should always be true */ in vk_optimize_depth_stencil_state()
746 assert(ds->stencil.write_enable); in vk_optimize_depth_stencil_state()
767 ds->depth.write_enable = false; in vk_optimize_depth_stencil_state()
775 ds->stencil.write_enable = false; in vk_optimize_depth_stencil_state()
787 ds->depth.write_enable = false; in vk_optimize_depth_stencil_state()
795 ds->depth.write_enable = false; in vk_optimize_depth_stencil_state()
804 ds->stencil.write_enable = false; in vk_optimize_depth_stencil_state()
809 if (ds->depth.compare_op == VK_COMPARE_OP_ALWAYS && !ds->depth.write_enable) in vk_optimize_depth_stencil_state()
[all...]
/third_party/libdrm/intel/
H A Dintel_bufmgr.h133 int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
198 void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
H A Dintel_bufmgr.c101 drm_intel_bo_map(drm_intel_bo *buf, int write_enable) in drm_intel_bo_map() argument
103 return buf->bufmgr->bo_map(buf, write_enable); in drm_intel_bo_map()
H A Dintel_bufmgr_priv.h114 int (*bo_map) (drm_intel_bo *bo, int write_enable);
H A Dintel_bufmgr_fake.c995 drm_intel_fake_bo_map_locked(drm_intel_bo *bo, int write_enable) in drm_intel_fake_bo_map_locked() argument
1043 if (write_enable) in drm_intel_fake_bo_map_locked()
1068 drm_intel_fake_bo_map(drm_intel_bo *bo, int write_enable) in drm_intel_fake_bo_map() argument
1075 ret = drm_intel_fake_bo_map_locked(bo, write_enable); in drm_intel_fake_bo_map()
H A Dintel_bufmgr_gem.c1403 static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) in drm_intel_gem_bo_map() argument
1453 if (write_enable) in drm_intel_gem_bo_map()
1466 if (write_enable) in drm_intel_gem_bo_map()
1937 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable) in drm_intel_gem_bo_start_gtt_access() argument
1947 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0; in drm_intel_gem_bo_start_gtt_access()
/third_party/mesa3d/src/panfrost/lib/
H A Dpan_cs.c474 cfg->write_enable = true; in pan_prepare_rt()
H A Dpan_blitter.c297 cfg.stencil_mask_misc.write_enable = true; in pan_blitter_emit_rsd()
/third_party/mesa3d/src/gallium/drivers/panfrost/
H A Dpan_cmdstream.c575 cfg.stencil_mask_misc.write_enable = !so->info[0].no_colour; in panfrost_prepare_fs_state()
/third_party/mesa3d/src/gallium/frontends/lavapipe/
H A Dlvp_execute.c750 state->dsa_state.depth_writemask = ps->ds->depth.write_enable; in handle_graphics_pipeline()

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