Home
last modified time | relevance | path

Searched refs:vtrn (Results 1 - 25 of 30) sorted by relevance

12

/third_party/ffmpeg/libavcodec/arm/
H A Dvp9lpf_16bpp_neon.S24 vswp \r1, \r8 @ vtrn.64 \rq0, \rq4
25 vswp \r3, \r10 @ vtrn.64 \rq1, \rq5
26 vswp \r5, \r12 @ vtrn.64 \rq2, \rq6
27 vswp \r7, \r14 @ vtrn.64 \rq3, \rq7
28 vtrn.32 \rq0, \rq2
29 vtrn.32 \rq1, \rq3
30 vtrn.32 \rq4, \rq6
31 vtrn.32 \rq5, \rq7
32 vtrn.16 \rq0, \rq1
33 vtrn
[all...]
H A Dvp3dsp_neon.S88 vtrn.8 d16, d17
89 vtrn.8 d18, d19
90 vtrn.16 d16, d18
91 vtrn.16 d17, d19
95 vtrn.8 d0, d1
241 vtrn.16 q8, q9
248 vtrn.16 q10, q11
249 vtrn.16 q12, q13
250 vtrn.16 q14, q15
251 vtrn
[all...]
H A Dh264idct_neon.S39 vtrn.16 d0, d1
40 vtrn.16 d3, d2
41 vtrn.32 d0, d3
42 vtrn.32 d1, d2
201 vtrn.32 q8, q10
202 vtrn.16 q12, q13
203 vtrn.32 q9, q11
204 vtrn.32 q12, q2
205 vtrn.32 q13, q15
250 vtrn
[all...]
H A Dh264cmc_neon.S241 vtrn.32 d4, d5
243 vtrn.32 d0, d1
244 vtrn.32 d2, d3
248 vtrn.32 d6, d7
253 vtrn.32 d4, d5
283 vtrn.32 d0, d1
320 vtrn.32 d4, d5
321 vtrn.32 d6, d7
391 vtrn.16 q0, q1
398 vtrn
[all...]
H A Dvp6dsp_neon.S102 vtrn.8 q8, q9
103 vtrn.8 q10, q11
104 vtrn.16 q8, q10
105 vtrn.16 q9, q11
107 vtrn.8 q9, q10
H A Drv34dsp_neon.S45 vtrn.32 q1, q2
46 vtrn.32 q3, q8
81 vtrn.32 q8, q9
86 vtrn.16 d16, d17
87 vtrn.32 d28, d29
88 vtrn.16 d18, d19
H A Dh264pred_neon.S138 vtrn.16 d4, d5
205 vtrn.32 d2, d3
217 vtrn.16 d4, d5
259 vtrn.32 d0, d1
279 vtrn.32 d0, d1
289 vtrn.32 q0, q2
305 vtrn.32 d0, d1
314 vtrn.32 q0, q2
335 vtrn.32 d0, d1
345 vtrn
[all...]
H A Dsimple_idct_neon.S126 vtrn.16 d2, d4
131 vtrn.16 d6, d8
134 vtrn.32 d2, d6
136 vtrn.32 d4, d8
141 vtrn.16 d3, d5
142 vtrn.16 d7, d9
143 vtrn.32 d3, d7
144 vtrn.32 d5, d9
H A Dh264dsp_neon.S250 vtrn.16 d18, d0
251 vtrn.16 d16, d2
252 vtrn.8 d18, d16
253 vtrn.8 d0, d2
257 vtrn.16 d18, d0
258 vtrn.16 d16, d2
259 vtrn.8 d18, d16
260 vtrn.8 d0, d2
H A Dvp8dsp_neon.S42 vtrn.32 d0, d2
43 vtrn.32 d1, d3
44 vtrn.16 d0, d1
45 vtrn.16 d2, d3
102 vtrn.32 d0, d3
103 vtrn.32 d1, d2
104 vtrn.16 d0, d1
105 vtrn.16 d3, d2
130 vtrn.32 q10, q11
135 vtrn
[all...]
H A Dhevcdsp_deblock_neon.S85 vtrn.16 q7, q4
86 vtrn.16 q6, q5
103 vtrn.32 q3, q4
137 vtrn.s16 q5, q2
146 vtrn.32 q2, q5
H A Daacpsdsp_neon.S183 vtrn.32 d6, d7
191 vtrn.32 q8, q9
192 vtrn.32 q1, q0
193 vtrn.32 q10, q11
H A Dvp9lpf_neon.S28 vtrn.32 \rq0, \rq2
29 vtrn.32 \rq1, \rq3
30 vtrn.16 \rq0, \rq1
31 vtrn.16 \rq2, \rq3
32 vtrn.8 \r0, \r1
33 vtrn.8 \r2, \r3
34 vtrn.8 \r4, \r5
35 vtrn.8 \r6, \r7
42 vtrn.16 \rq0, \rq1
43 vtrn
[all...]
H A Dsbrdsp_neon.S220 vtrn.32 d0, d1
222 vtrn.32 d18, d1
291 vtrn.32 d1, d3
295 vtrn.32 d0, d6
H A Drv40dsp_neon.S753 vtrn.16 d16, d17
764 vtrn.32 d18, d19
806 vtrn.16 d0, d1
839 vtrn.32 d4, d5 @ -3, 2, -1, 0
862 vtrn.32 d0, d1 @ -2, 1, -2, 1
900 vtrn.16 q2, q1
901 vtrn.8 d4, d5
902 vtrn.8 d2, d3
905 vtrn.32 q2, q1
911 vtrn
[all...]
H A Drdft_neon.S67 vtrn.32 d16, d17
129 vtrn.32 d22, d23
H A Dvc1dsp_neon.S38 vtrn.16 \r0, \r1 @ first and second row
39 vtrn.16 \r2, \r3 @ third and fourth row
40 vtrn.32 \r0, \r2 @ first and third row
41 vtrn.32 \r1, \r3 @ second and fourth row
1252 vtrn.8 q1, q2
1253 vtrn.16 d2, d3 @ P1, P5, P3, P7
1254 vtrn.16 d4, d5 @ P2, P6, P4, P8
1406 vtrn.8 q1, q2 @ P1[0], P1[1], P3[0]... P1[2], P1[3], P3[2]... P2[0], P2[1], P4[0]... P2[2], P2[3], P4[2]...
1408 vtrn.16 d2, d3 @ P1[0], P1[1], P1[2], P1[3], P5[0]... P3[0], P3[1], P3[2], P3[3], P7[0]...
1409 vtrn
[all...]
/third_party/ffmpeg/libswscale/arm/
H A Drgb2yuv_neon_32.S66 vtrn.u8 \s8x16, n16x16_o
89 vtrn.8 y16x16_e, y16x16_o
/third_party/node/deps/openssl/openssl/crypto/poly1305/asm/
H A Dpoly1305-armv4.pl614 vtrn.32 $R0,$D0#lo @ r^2:r^1
615 vtrn.32 $R2,$D2#lo
616 vtrn.32 $R3,$D3#lo
617 vtrn.32 $R1,$D1#lo
618 vtrn.32 $R4,$D4#lo
/third_party/openssl/crypto/poly1305/asm/
H A Dpoly1305-armv4.pl614 vtrn.32 $R0,$D0#lo @ r^2:r^1
615 vtrn.32 $R2,$D2#lo
616 vtrn.32 $R3,$D3#lo
617 vtrn.32 $R1,$D1#lo
618 vtrn.32 $R4,$D4#lo
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h979 void vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2);
980 void vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2);
H A Dassembler-arm.cc4968 if (size == Neon32) { // vzip.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm. in vzip()
4969 vtrn(size, src1, src2); in vzip()
4986 if (size == Neon32) { // vuzp.32 Dd, Dm is a pseudo-op for vtrn.32 Dd, Dm. in vuzp()
4987 vtrn(size, src1, src2); in vuzp()
5024 void Assembler::vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) { in vtrn() function in v8::internal::Assembler
5026 // vtrn.<size>(Dn, Dm) SIMD element transpose. in vtrn()
5031 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) { in vtrn() function in v8::internal::Assembler
5033 // vtrn.<size>(Qn, Qm) SIMD element transpose. in vtrn()
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc2298 Format(instr, q ? "vtrn.'size2 'Qd, 'Qm" : "vtrn.'size2 'Dd, 'Dm"); in DecodeAdvancedSIMDTwoOrThreeRegisters()
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.h6117 void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm);
6118 void vtrn(DataType dt, DRegister rd, DRegister rm) { vtrn(al, dt, rd, rm); } in vtrn() function in vixl::aarch32::Assembler
6120 void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm);
6121 void vtrn(DataType dt, QRegister rd, QRegister rm) { vtrn(al, dt, rd, rm); } in vtrn() function in vixl::aarch32::Assembler
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc2082 // Move left and right into temporaries, they will be modified by vtrn. in AssembleArchInstruction()
2098 __ vtrn(Neon32, tmp1.low(), tmp1.high()); in AssembleArchInstruction()
2100 __ vtrn(Neon32, tmp2.low(), tmp2.high()); in AssembleArchInstruction()
2907 __ vtrn(Neon32, dst.low(), dst.high()); // dst = [0, 4, 1, 5] in AssembleArchInstruction()
2916 __ vtrn(Neon32, dst.low(), dst.high()); // dst = [2, 6, 3, 7] in AssembleArchInstruction()
2949 __ vtrn(Neon32, dst, scratch); // dst = [0, 4, 2, 6] in AssembleArchInstruction()
2983 __ vtrn(Neon32, scratch, dst); // dst = [1, 5, 3, 7] in AssembleArchInstruction()
3034 __ vtrn(Neon16, dst, scratch); // dst = [0, 8, 2, 10, ... 14] in AssembleArchInstruction()
3045 __ vtrn(Neon16, scratch, dst); // dst = [1, 9, 3, 11, ... 15] in AssembleArchInstruction()
3096 __ vtrn(Neon in AssembleArchInstruction()
[all...]

Completed in 61 milliseconds

12