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Searched refs:tess_rings (Results 1 - 7 of 7) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_gfx_cs.c119 if (ctx->gfx_level == GFX11 && ctx->tess_rings) { in si_flush_gfx_cs()
428 if (ctx->tess_rings) { in si_begin_new_gfx_cs()
430 unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings), in si_begin_new_gfx_cs()
H A Dsi_state_shaders.cpp4077 assert(!sctx->tess_rings);
4082 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
4091 if (!sctx->tess_rings)
4108 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->hs.tess_offchip_ring_size;
4123 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(sctx->tess_rings),
4149 struct pipe_resource *tf_ring = tmz ? sctx->tess_rings_tmz : sctx->tess_rings;
H A Dsi_state_draw.cpp123 if (!sctx->tess_rings) { in si_update_shaders()
125 if (!sctx->tess_rings) in si_update_shaders()
774 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address;
H A Dsi_pipe.h1101 struct pipe_resource *tess_rings; member
H A Dsi_pipe.c212 pipe_resource_reference(&sctx->tess_rings, NULL); in si_destroy_context()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_device.c4409 if (!queue->ring_info.tess_rings && needs->tess_rings) { in radv_update_preamble_cs()
4531 !needs->esgs_ring_size && !needs->gsvs_ring_size && !needs->tess_rings && in radv_update_preamble_cs()
4912 needs.tess_rings |= cmd_buffer->tess_rings_needed; in radv_update_preambles()
4941 queue->ring_info.tess_rings == needs.tess_rings && in radv_update_preambles()
H A Dradv_private.h735 bool tess_rings;

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