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Searched refs:spilled (Results 1 - 17 of 17) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
H A Dtest_simd_selection.cpp39 const bool spilled = true; variable
99 brw_simd_mark_compiled(SIMD32, prog_data, spilled); in TEST_F()
164 brw_simd_mark_compiled(SIMD8, prog_data, spilled); in TEST_F()
166 brw_simd_mark_compiled(SIMD16, prog_data, spilled); in TEST_F()
168 brw_simd_mark_compiled(SIMD32, prog_data, spilled); in TEST_F()
256 brw_simd_mark_compiled(SIMD8, prog_data, spilled); in TEST_F()
268 brw_simd_mark_compiled(SIMD16, prog_data, spilled); in TEST_F()
297 brw_simd_mark_compiled(SIMD32, prog_data, spilled); in TEST_F()
H A Dbrw_simd_selection.c133 brw_simd_mark_compiled(unsigned simd, struct brw_cs_prog_data *prog_data, bool spilled) in brw_simd_mark_compiled() argument
139 /* If a SIMD spilled, all the larger ones would spill too. */ in brw_simd_mark_compiled()
140 if (spilled) { in brw_simd_mark_compiled()
H A Dbrw_private.h45 bool spilled);
H A Dbrw_fs_reg_allocate.cpp437 * variable size that can be spilled -- A higher value will allow a
438 * variable of a given size to be spilled more efficiently with a smaller
445 * component type and natural region width can be spilled without splitting
1079 * spilled. Right now, we spill or unspill the whole thing to a in spill_reg()
1109 * correspondence between channels of the spilled variable in in spill_reg()
1139 * channels per spilled register). We attempt to write one in spill_reg()
1198 bool spilled = false; in assign_regs() local
1222 /* If we're going to spill but we've never spilled before, we need to in assign_regs()
1230 spilled = true; in assign_regs()
1235 if (spilled) in assign_regs()
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/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Dregalloc.c248 alu_dest->ssa.spilled = true; in ppir_update_spilled_src()
423 if (reg->spilled) { in ppir_regalloc_choose_spill_node()
488 chosen->spilled = true; in ppir_regalloc_choose_spill_node()
535 static bool ppir_regalloc_prog_try(ppir_compiler *comp, bool *spilled) in ppir_regalloc_prog_try() argument
562 *spilled = false; in ppir_regalloc_prog_try()
574 *spilled = true; in ppir_regalloc_prog_try()
576 ppir_debug("spilled register %d/%d, num_components: %d\n", in ppir_regalloc_prog_try()
610 bool spilled = false; in ppir_regalloc_prog() local
629 while (!ppir_regalloc_prog_try(comp, &spilled)) in ppir_regalloc_prog()
630 if (!spilled) in ppir_regalloc_prog()
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H A Dppir.h229 bool spilled; member
/third_party/node/deps/v8/src/compiler/backend/
H A Dregister-allocator.cc63 // connecting moves for spilled ranges. in Initialize()
65 new (curr) LiveRangeBound(i, i->spilled()); in Initialize()
337 DCHECK(!HasRegisterAssigned() && !spilled()); in set_assigned_register()
342 DCHECK(HasRegisterAssigned() && !spilled()); in UnsetAssignedRegister()
369 DCHECK(spilled()); in Unspill()
375 DCHECK(!spilled()); in Spill()
498 DCHECK(!spilled()); in GetAssignedOperand()
502 DCHECK(spilled()); in GetAssignedOperand()
858 bool might_be_duplicated = has_slot_use() || spilled(); in FilterSpillMoves()
1140 if (range->spilled()) { in PrintRangeRow()
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H A Dspill-placer.cc37 // - If the first LiveRange is spilled, then there's no sense in doing in Add()
41 // incorrect behavior, so the value must be spilled at the definition. in Add()
47 range->spilled() || top_start_block->IsDeferred() || in Add()
54 // spilled. in Add()
57 if (child->spilled()) { in Add()
426 // spilled, then the value should be spilled at the definition. in SecondBackwardPass()
H A Dmid-tier-register-allocator.cc288 // and tracks spilled operands for that virtual register.
349 // Returns true if the virtual register should be spilled when it is output.
358 // Returns true if the virtual register should be spilled at entry to deferred
359 // blocks in which it is spilled (to avoid spilling on output on
400 // to be spilled on the stack.
773 // spill gap move, if the register never gets spilled in a non-deferred block.
779 // never spilled in a non-deferred block.
785 // If the register is later spilled, a gap move will be added immediately
828 // blocks and was spilled in those blocks.
839 // currently holding, and how it should be updated if committed or spilled
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H A Dregister-allocator.h575 bool spilled() const { return SpilledField::decode(bits_); } in spilled() function in v8::internal::compiler::RegisterAllocationFlag::LiveRange
612 // Can this live range be spilled at this position.
862 // kSpillRange: copied (spilled) to memory location at the definition,
865 // kDeferredSpillRange: copied (spilled) to memory location at entry
869 // state, or kNoSpillType. When spilled only in deferred code, a range
870 // ends up with kDeferredSpillRange, while when spilled in regular code,
923 // If all the children of this range are spilled in deferred blocks, and if
924 // for any non-spilled child with a use position requiring a slot, that range
928 // deferred blocks. If so, we insert here spills for non-spilled ranges
939 // spilled a
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/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_ra.c449 allocate_registers(compiler_context *ctx, bool *spilled) in allocate_registers() argument
719 *spilled = !lcra_solve(l); in allocate_registers()
870 /* We can't spill a previously spilled value or an unspill */ in mir_choose_spill_node()
923 /* For TLS, replace all stores to the spilled node. For in mir_spill_register()
1025 * use of the node, rewriting to use spilled indices to in mir_spill_register()
1040 /* If we don't use the spilled value, nothing to do */ in mir_spill_register()
1068 /* Special writes already have their move spilled in */ in mir_spill_register()
1146 bool spilled = false; in mir_ra() local
1149 /* Number of 128-bit slots in memory we've spilled into */ in mir_ra()
1156 if (spilled) { in mir_ra()
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/third_party/mesa3d/src/amd/compiler/
H A Daco_spill.cpp488 /* first block, nothing was spilled before */ in init_live_in_vars()
503 /* check how many live-through variables should be spilled */ in init_live_in_vars()
513 for (auto spilled : ctx.spills_exit[block_idx - 1]) { in init_live_in_vars()
514 auto it = next_use_distances.find(spilled.first); in init_live_in_vars()
520 /* keep constants and live-through variables spilled */ in init_live_in_vars()
521 if (it->second.first >= loop_end || ctx.remat.count(spilled.first)) { in init_live_in_vars()
522 ctx.spills_entry[block_idx][spilled.first] = spilled.second; in init_live_in_vars()
523 spilled_registers += spilled.first; in init_live_in_vars()
524 loop_demand -= spilled in init_live_in_vars()
889 auto spilled = ctx.spills_exit[pred_idx].find(var); add_coupling_code() local
941 auto spilled = ctx.spills_exit[pred_idx].find(pair.first); add_coupling_code() local
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/third_party/node/deps/v8/src/compiler/
H A Dgraph-visualizer.cc746 } else if (range->spilled()) { in PrintLiveRange()
966 } else if (range.spilled() && !range.TopLevel()->HasNoSpillType()) { in operator <<()
974 os << "\"spilled\",\"op\":"; in operator <<()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_shader.c420 /* flag for each tgsi temp array if its been spilled or not */
992 bool *spilled = ctx->spilled_arrays; // assumed calloc:ed in choose_spill_arrays() local
1002 if (!spilled[i] && size > largest) { in choose_spill_arrays()
1008 spilled[largest_index] = true; in choose_spill_arrays()
1020 /* Take spilled temp arrays into account when translating tgsi register
1021 * indexes into r600 gprs if spilled is false, or scratch array offset if
1022 * spilled is true */
1023 static int map_tgsi_reg_index_to_r600_gpr(struct r600_shader_ctx *ctx, unsigned tgsi_reg_index, bool *spilled) in map_tgsi_reg_index_to_r600_gpr() argument
1031 /* vec4 index into spilled scratch memory */ in map_tgsi_reg_index_to_r600_gpr()
1032 *spilled in map_tgsi_reg_index_to_r600_gpr()
1176 bool spilled; tgsi_declaration() local
1624 bool spilled; tgsi_src() local
4431 bool spilled; tgsi_dst() local
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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_ra.c2595 bool spilled = false; in ir3_ra() local
2607 spilled = true; in ir3_ra()
2661 if (spilled) { in ir3_ra()
/third_party/node/deps/v8/src/wasm/baseline/
H A Dliftoff-compiler.cc172 // All register values will be spilled before the pc covered by the debug
178 // Register slots cannot appear since we already spilled.
2755 auto* spilled = compilation_zone_->New<SpilledRegistersForInspection>(
2760 spilled->entries.push_back(SpilledRegistersForInspection::Entry{
2764 return spilled;
4518 // register and let go of the value register to get spilled.
/third_party/skia/third_party/externals/microhttpd/doc/
H A Dtexinfo.tex8358 % Deeper inside, just make sure that the saved insertions are not spilled

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