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Searched refs:reg3 (Results 1 - 25 of 43) sorted by relevance

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/third_party/ffmpeg/libavcodec/loongarch/
H A Dvp9_idct_lsx.c377 __m128i reg1, reg3, reg5, reg7, reg9, reg11, reg13, reg15; in vp9_idct16_1d_columns_addblk_lsx() local
383 reg0, reg1, reg2, reg3); in vp9_idct16_1d_columns_addblk_lsx()
435 VP9_DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1); in vp9_idct16_1d_columns_addblk_lsx()
436 LSX_BUTTERFLY_4_H(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vp9_idct16_1d_columns_addblk_lsx()
438 loc1 = __lsx_vadd_h(reg15, reg3); in vp9_idct16_1d_columns_addblk_lsx()
439 reg3 = __lsx_vsub_h(reg15, reg3); in vp9_idct16_1d_columns_addblk_lsx()
472 VP9_DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13); in vp9_idct16_1d_columns_addblk_lsx()
473 LSX_BUTTERFLY_4_H(reg12, reg14, reg13, reg3, reg in vp9_idct16_1d_columns_addblk_lsx()
501 __m128i reg1, reg3, reg5, reg7, reg9, reg11, reg13, reg15; vp9_idct16_1d_columns_lsx() local
883 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
998 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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H A Dh264_intrapred_lasx.c30 __m256i reg0, reg1, reg2, reg3, reg4; \
74 reg3 = __lasx_xvmul_w(reg0, int_mult1); \
76 reg4 = __lasx_xvadd_w(reg4, reg3); \
78 tmp0 = __lasx_xvadd_w(reg2, reg3); \
83 tmp2 = __lasx_xvadd_w(reg2, reg3); \
H A Dvp9_mc_lsx.c457 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
486 DUP2_ARG2(__lsx_vilvl_d, tmp1, tmp0, tmp3, tmp2, reg3, reg4); in common_vt_8t_4w_lsx()
487 DUP2_ARG2(__lsx_vxori_b, reg3, 128, reg4, 128, reg3, reg4); in common_vt_8t_4w_lsx()
488 out0 = FILT_8TAP_DPADD_S_H(reg0, reg1, reg2, reg3, filter0, filter1, in common_vt_8t_4w_lsx()
490 out1 = FILT_8TAP_DPADD_S_H(reg1, reg2, reg3, reg4, filter0, filter1, in common_vt_8t_4w_lsx()
504 reg1 = reg3; in common_vt_8t_4w_lsx()
517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
541 reg0, reg1, reg2, reg3); in common_vt_8t_8w_lsx()
555 out1 = FILT_8TAP_DPADD_S_H(reg3, reg in common_vt_8t_8w_lsx()
589 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_lsx() local
683 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_mult_lsx() local
1543 __m128i reg0, reg1, reg2, reg3, reg4; common_vt_8t_and_aver_dst_4w_lsx() local
1619 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_8w_lsx() local
1705 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_16w_mult_lsx() local
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H A Dhevc_mc_bi_lsx.c64 __m128i reg0, reg1, reg2, reg3; in hevc_bi_copy_4w_lsx() local
71 reg3 = __lsx_vldrepl_w(src0_ptr + src_stride_3x, 0); in hevc_bi_copy_4w_lsx()
73 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1); in hevc_bi_copy_4w_lsx()
78 reg3 = __lsx_vldrepl_w(src0_ptr + src_stride_3x, 0); in hevc_bi_copy_4w_lsx()
79 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1); in hevc_bi_copy_4w_lsx()
115 reg3 = __lsx_vldrepl_d(src1_ptr + src2_stride, 0); in hevc_bi_copy_4w_lsx()
117 in0 = __lsx_vilvl_d(reg3, reg2); in hevc_bi_copy_4w_lsx()
150 __m128i reg0, reg1, reg2, reg3; in hevc_bi_copy_6w_lsx() local
156 reg3 = __lsx_vldrepl_d(src0_ptr + src_stride_3x, 0); in hevc_bi_copy_6w_lsx()
157 DUP2_ARG2(__lsx_vilvl_d, reg1, reg0, reg3, reg in hevc_bi_copy_6w_lsx()
246 __m128i reg0, reg1, reg2, reg3; hevc_bi_copy_8w_lsx() local
1507 __m128i reg0, reg1, reg2, reg3; hevc_hv_4t_6w_lsx() local
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H A Dvc1dsp_lasx.c144 __m256i reg0, reg1, reg2, reg3; in ff_vc1_inv_trans_8x8_dc_lasx() local
161 const_dc, temp3, const_dc, reg0, reg1, reg2, reg3); in ff_vc1_inv_trans_8x8_dc_lasx()
162 DUP2_ARG3(__lasx_xvssrarni_bu_h, reg1, reg0, 0, reg3, reg2, 0, in ff_vc1_inv_trans_8x8_dc_lasx()
/third_party/node/deps/openssl/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
492 reg3 = GET_U32_BE(in, 3); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
526 reg3 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
492 reg3 = GET_U32_BE(in, 3); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
526 reg3 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h975 const CPURegister& reg3 = NoReg,
989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1031 const CPURegister& reg3 = NoCPUReg,
1040 match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
1055 const CPURegister& reg3 = NoReg,
1064 even &= !reg3.IsValid() || ((reg3.GetCode() % 2) == 0);
1080 const CPURegister& reg3 = NoCPUReg,
1091 if (!reg3
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H A Dmacro-assembler-aarch64.cc3104 const Register& reg3, in Emit()
3108 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3118 const VRegister& reg3, in Emit()
3121 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3128 const CPURegister& reg3, in Emit()
3134 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Emit()
3168 const Register& reg3, in Emit()
3171 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3178 const VRegister& reg3, in Emit()
3181 reg1.GetBit() | reg2.GetBit() | reg3 in Emit()
3102 Include(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) Emit() argument
3116 Include(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) Emit() argument
3126 Include(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) Emit() argument
3166 Exclude(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) Emit() argument
3176 Exclude(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) Emit() argument
3186 Exclude(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) Emit() argument
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H A Doperands-aarch64.h44 CPURegister reg3 = NoCPUReg, in CPURegList()
46 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()), in CPURegList()
49 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4)); in CPURegList()
/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-register.cc105 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, in AreContiguous() argument
110 if (reg3.is_valid() && reg2.index() + 1 != reg3.index()) { in AreContiguous()
113 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
H A Dbytecode-register.h86 Register reg3 = invalid_value(),
/third_party/ffmpeg/libavcodec/mips/
H A Dvp9_idct_msa.c968 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
1008 VP9_DOTP_CONST_PAIR(reg13, reg3, cospi_6_64, cospi_26_64, loc0, loc1); in vp9_idct16_1d_columns_addblk_msa()
1009 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vp9_idct16_1d_columns_addblk_msa()
1011 loc1 = reg15 + reg3; in vp9_idct16_1d_columns_addblk_msa()
1012 reg3 = reg15 - reg3; in vp9_idct16_1d_columns_addblk_msa()
1045 VP9_DOTP_CONST_PAIR(reg3, reg13, cospi_16_64, cospi_16_64, reg3, reg13); in vp9_idct16_1d_columns_addblk_msa()
1046 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg in vp9_idct16_1d_columns_addblk_msa()
1071 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; vp9_idct16_1d_columns_msa() local
1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
[all...]
H A Dh264pred_msa.c217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
268 reg3 = reg2 + vec6; in intra_predict_plane_16x16_msa()
271 SRA_4V(reg0, reg1, reg2, reg3, 5); in intra_predict_plane_16x16_msa()
273 PCKEV_H2_SH(reg1, reg0, reg3, reg2, vec11, vec12); in intra_predict_plane_16x16_msa()
/third_party/ffmpeg/libavcodec/aarch64/
H A Dvp9mc_16bpp_neon.S326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
329 sqrshrun \reg3\().4h, \reg3\().4s, #7
339 umin \reg3\().4h, \reg3\().4h, \minreg\().4h
344 urhadd \reg3\().4h, \reg3\().4h, \tmp3\().4h
349 st1 {\reg3\().4h}, [x0], x1
354 // reg1-2, reg3-4 etc pairwise correspond to 4 rows.
355 .macro do_store8 reg1, reg2, reg3, reg
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H A Dvp9mc_neon.S407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
410 sqrshrun \reg3\().8b, \reg3\().8h, #7
419 urhadd \reg3\().8b, \reg3\().8b, \tmp3\().8b
424 st1 {\reg3\().8b}, [x0], x1
/third_party/mesa3d/src/panfrost/bifrost/
H A Ddisassemble.c152 else if (regs.reg2 == regs.reg3) in DecodeRegCtrl()
183 fprintf(fp, "slot 3: r%u (write %s) ", srcs.reg3, slot3_fma); in dump_regs()
185 fprintf(fp, "slot 3: r%u (write lo %s) ", srcs.reg3, slot3_fma); in dump_regs()
187 fprintf(fp, "slot 3: r%u (write hi %s) ", srcs.reg3, slot3_fma); in dump_regs()
213 fprintf(fp, "r%u:t0", next_regs->reg3); in bi_disasm_dest_fma()
226 fprintf(fp, "r%u:t1", next_regs->reg3); in bi_disasm_dest_add()
H A Dbifrost.h228 unsigned reg3 : 6; member
H A Dbi_pack.c268 s.reg3 = regs.slot[3]; in bi_pack_registers()
/third_party/musl/src/thread/powerpc/
H A D__set_thread_area.s6 # mov pointer in reg3 into r2
/third_party/node/deps/v8/src/codegen/arm64/
H A Dregister-arm64.h515 const CPURegister& reg3 = NoReg, const CPURegister& reg4 = NoReg,
525 const CPURegister& reg3 = NoCPUReg, const CPURegister& reg4 = NoCPUReg,
533 const VRegister& reg3 = NoVReg,
542 const VRegister& reg3 = NoVReg,
H A Dassembler-arm64.cc225 const CPURegister& reg3, const CPURegister& reg4, in AreAliased()
234 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
261 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType()
267 match &= !reg3.is_valid() || reg3.IsSameSizeAndType(reg1); in AreSameSizeAndType()
277 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat()
280 (!reg3.is_valid() || reg3.IsSameFormat(reg1)) && in AreSameFormat()
285 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive()
288 DCHECK(!reg3 in AreConsecutive()
224 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) AreAliased() argument
260 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) AreSameSizeAndType() argument
276 AreSameFormat(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) AreSameFormat() argument
284 AreConsecutive(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) AreConsecutive() argument
[all...]
/third_party/vixl/src/aarch32/
H A Dinstructions-aarch32.h467 constexpr RegisterList(Register reg1, Register reg2, Register reg3)
469 RegisterToList(reg3)) {}
470 constexpr RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
472 RegisterToList(reg3) | RegisterToList(reg4)) {}
558 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3)
560 RegisterToList(reg3)) {}
561 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4)
563 RegisterToList(reg3) | RegisterToList(reg4)) {}
H A Dmacro-assembler-aarch32.cc453 CPURegister reg3, in Printf()
463 PushRegister(reg3); in Printf()
476 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) | in Printf()
481 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() + in Printf()
502 if (reg3.GetType() == CPURegister::kRRegister) { in Printf()
503 available_registers.Remove(Register(reg3.GetCode())); in Printf()
517 PushRegister(reg3); in Printf()
528 PreparePrintfArgument(reg3, &core_count, &vfp_count, &printf_type); in Printf()
450 Printf(const char* format, CPURegister reg1, CPURegister reg2, CPURegister reg3, CPURegister reg4) Printf() argument
/third_party/ffmpeg/libavcodec/x86/
H A Dhevc_mc.asm522 %define %%reg3 %8
527 %define %%reg3 m3
547 pmaddubsw %%reg3, %4
548 paddw %%reg1, %%reg3
556 pmaddwd %%reg3, %4
557 paddd %%reg1, %%reg3

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