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/third_party/ffmpeg/libavcodec/loongarch/
H A Dh264_intrapred_lasx.c30 __m256i reg0, reg1, reg2, reg3, reg4; \
48 reg0 = __lasx_xvldx(src0, -stride); \
50 reg0 = __lasx_xvilvl_d(reg1, reg0); \
51 reg0 = __lasx_xvshuf_b(reg0, reg0, shuff); \
52 reg0 = __lasx_xvhsubw_hu_bu(reg0, reg0); \
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H A Dvp9_intra_lsx.c435 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1; in ff_tm_4x4_lsx() local
439 reg0 = __lsx_vreplgr2vr_h(top_left); in ff_tm_4x4_lsx()
447 DUP4_ARG2(__lsx_vssub_hu, dst0, reg0, dst1, reg0, dst2, reg0, dst3, reg0, in ff_tm_4x4_lsx()
467 __m128i reg0, reg1; in ff_tm_8x8_lsx() local
469 reg0 = __lsx_vreplgr2vr_h(top_left); in ff_tm_8x8_lsx()
483 DUP4_ARG2(__lsx_vssub_hu, src0, reg0, src1, reg0, src in ff_tm_8x8_lsx()
517 __m128i reg0, reg1; ff_tm_16x16_lsx() local
600 __m128i tmp0, tmp1, tmp2, tmp3, reg0, reg1, reg2; ff_tm_32x32_lsx() local
[all...]
H A Dvp9_idct_lsx.c68 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
76 s1_m = __lsx_vilvl_h(__lsx_vneg_h(reg1), reg0); \
77 s0_m = __lsx_vilvh_h(__lsx_vneg_h(reg1), reg0); \
78 s3_m = __lsx_vilvl_h(reg0, reg1); \
79 s2_m = __lsx_vilvh_h(reg0, reg1); \
376 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_lsx() local
383 reg0, reg1, reg2, reg3); in vp9_idct16_1d_columns_addblk_lsx()
412 VP9_DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vp9_idct16_1d_columns_addblk_lsx()
414 LSX_BUTTERFLY_4_H(reg8, reg0, reg in vp9_idct16_1d_columns_addblk_lsx()
502 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; vp9_idct16_1d_columns_lsx() local
883 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
998 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
[all...]
H A Dhevc_mc_bi_lsx.c64 __m128i reg0, reg1, reg2, reg3; in hevc_bi_copy_4w_lsx() local
68 reg0 = __lsx_vldrepl_w(src0_ptr, 0); in hevc_bi_copy_4w_lsx()
73 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1); in hevc_bi_copy_4w_lsx()
75 reg0 = __lsx_vldrepl_w(src0_ptr, 0); in hevc_bi_copy_4w_lsx()
79 DUP2_ARG2(__lsx_vilvl_w, reg1, reg0, reg3, reg2, tmp0, tmp1); in hevc_bi_copy_4w_lsx()
112 reg0 = __lsx_vldrepl_w(src0_ptr, 0); in hevc_bi_copy_4w_lsx()
116 src0 = __lsx_vilvl_w(reg1, reg0); in hevc_bi_copy_4w_lsx()
150 __m128i reg0, reg1, reg2, reg3; in hevc_bi_copy_6w_lsx() local
153 reg0 = __lsx_vldrepl_d(src0_ptr, 0); in hevc_bi_copy_6w_lsx()
157 DUP2_ARG2(__lsx_vilvl_d, reg1, reg0, reg in hevc_bi_copy_6w_lsx()
246 __m128i reg0, reg1, reg2, reg3; hevc_bi_copy_8w_lsx() local
1507 __m128i reg0, reg1, reg2, reg3; hevc_hv_4t_6w_lsx() local
[all...]
H A Dvp9_mc_lsx.c457 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
474 DUP2_ARG2(__lsx_vilvl_d, tmp3, tmp0, tmp4, tmp1, reg0, reg1); in common_vt_8t_4w_lsx()
476 DUP2_ARG2(__lsx_vxori_b, reg0, 128, reg1, 128, reg0, reg1); in common_vt_8t_4w_lsx()
488 out0 = FILT_8TAP_DPADD_S_H(reg0, reg1, reg2, reg3, filter0, filter1, in common_vt_8t_4w_lsx()
503 reg0 = reg2; in common_vt_8t_4w_lsx()
517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
541 reg0, reg1, reg2, reg3); in common_vt_8t_8w_lsx()
553 out0 = FILT_8TAP_DPADD_S_H(reg0, reg1, reg2, tmp0, filter0, filter1, in common_vt_8t_8w_lsx()
572 reg0 in common_vt_8t_8w_lsx()
589 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_lsx() local
683 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_mult_lsx() local
1543 __m128i reg0, reg1, reg2, reg3, reg4; common_vt_8t_and_aver_dst_4w_lsx() local
1619 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_8w_lsx() local
1705 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_16w_mult_lsx() local
[all...]
H A Dvc1dsp_lasx.c144 __m256i reg0, reg1, reg2, reg3; in ff_vc1_inv_trans_8x8_dc_lasx() local
161 const_dc, temp3, const_dc, reg0, reg1, reg2, reg3); in ff_vc1_inv_trans_8x8_dc_lasx()
162 DUP2_ARG3(__lasx_xvssrarni_bu_h, reg1, reg0, 0, reg3, reg2, 0, in ff_vc1_inv_trans_8x8_dc_lasx()
272 __m256i const_dc, temp0, temp1, reg0, reg1; in ff_vc1_inv_trans_8x4_dc_lasx() local
282 DUP2_ARG2(__lasx_xvadd_h, temp0, const_dc, temp1, const_dc, reg0, reg1); in ff_vc1_inv_trans_8x4_dc_lasx()
283 temp0 = __lasx_xvssrarni_bu_h(reg1, reg0, 0); in ff_vc1_inv_trans_8x4_dc_lasx()
298 __m256i const_dc, temp0, temp1, temp2, temp3, reg0, reg1; in ff_vc1_inv_trans_4x8_dc_lasx() local
311 DUP2_ARG2(__lasx_xvilvl_d, temp1, temp0, temp3, temp2, reg0, reg1); in ff_vc1_inv_trans_4x8_dc_lasx()
312 DUP2_ARG1(__lasx_vext2xv_hu_bu, reg0, reg1, temp0, temp1); in ff_vc1_inv_trans_4x8_dc_lasx()
313 DUP2_ARG2(__lasx_xvadd_h, temp0, const_dc, temp1, const_dc, reg0, reg in ff_vc1_inv_trans_4x8_dc_lasx()
[all...]
/third_party/node/deps/openssl/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
489 reg0 = GET_U32_BE(in, 0); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
511 reg0 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
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/third_party/openssl/crypto/aria/
H A Daria.c474 register uint32_t reg0, reg1, reg2, reg3; in ossl_aria_encrypt() local
489 reg0 = GET_U32_BE(in, 0); in ossl_aria_encrypt()
494 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
497 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
498 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
502 ARIA_SUBST_DIFF_EVEN(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
503 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
506 ARIA_SUBST_DIFF_ODD(reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
507 ARIA_ADD_ROUND_KEY(rk, reg0, reg1, reg2, reg3); in ossl_aria_encrypt()
511 reg0 in ossl_aria_encrypt()
541 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_encrypt_key() local
676 register uint32_t reg0, reg1, reg2, reg3; ossl_aria_set_decrypt_key() local
[all...]
/third_party/mesa3d/src/gallium/drivers/r600/sfn/tests/
H A Dsfn_value_test.cpp92 UniformValue reg0(512, 1); in TEST_F()
94 EXPECT_EQ(reg0.sel(), 512); in TEST_F()
95 EXPECT_EQ(reg0.chan(), 1); in TEST_F()
96 EXPECT_EQ(reg0.kcache_bank(), 0); in TEST_F()
97 EXPECT_FALSE(reg0.buf_addr()); in TEST_F()
98 EXPECT_FALSE(reg0.is_virtual()); in TEST_F()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dreglist-arm64.h28 explicit CPURegList(CPURegister reg0, CPURegisters... regs) in CPURegList() argument
29 : list_(((uint64_t{1} << reg0.code()) | ... | in CPURegList()
31 size_(reg0.SizeInBits()),
32 type_(reg0.type()) {
33 DCHECK(AreSameSizeAndType(reg0, regs...));
/third_party/ffmpeg/libavcodec/mips/
H A Dvp9_idct_msa.c67 #define VP9_DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) \
75 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
76 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
985 VP9_DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
989 reg0 = reg2 - loc1; in vp9_idct16_1d_columns_addblk_msa()
1018 loc0 = reg0 in vp9_idct16_1d_columns_addblk_msa()
1070 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; vp9_idct16_1d_columns_msa() local
1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
[all...]
H A Dh264pred_msa.c217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa() local
259 reg0 = vec7; in intra_predict_plane_16x16_msa()
262 reg0 += vec4; in intra_predict_plane_16x16_msa()
264 reg1 = reg0 + vec6; in intra_predict_plane_16x16_msa()
271 SRA_4V(reg0, reg1, reg2, reg3, 5); in intra_predict_plane_16x16_msa()
273 PCKEV_H2_SH(reg1, reg0, reg3, reg2, vec11, vec12); in intra_predict_plane_16x16_msa()
/third_party/mesa3d/src/gallium/drivers/r600/
H A Degd_tables.py207 reg0 = reg_dict.get(match_number.sub('0', reg.name))
208 if reg0 != None:
209 reg.fields = reg0.fields
210 reg.fields_owner = reg0
/third_party/mesa3d/src/freedreno/decode/
H A Dcrashdec-mempool.c56 uint32_t reg0 : 18; in dump_mem_pool_chunk() member
68 dump_mem_pool_reg_write(fields.reg0, fields.data0, fields.reg0_context, in dump_mem_pool_chunk()
/third_party/mesa3d/src/panfrost/bifrost/
H A Ddisassemble.c59 return regs.reg0 | ((regs.reg1 & 0x1) << 5); in get_reg0()
61 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0; in get_reg0()
66 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1; in get_reg1()
H A Dbi_pack.c236 s.reg0 = regs.slot[0]; in bi_pack_registers()
247 s.reg0 = (regs.slot[0] & 0b11111); in bi_pack_registers()
H A Dbifrost.h230 unsigned reg0 : 5; member
/third_party/backends/backend/
H A Dp5_device.c723 uint8_t reg0=0; in start_scan() local
779 reg0 = 0x00; in start_scan()
784 reg0 = 0x20; in start_scan()
788 reg0 = 0x40; in start_scan()
795 write_reg (dev->fd, REG0, reg0); in start_scan()
831 write_reg (dev->fd, REG0, reg0); in start_scan()
843 write_reg (dev->fd, REG0, reg0 | 0x0C); in start_scan()
/third_party/mesa3d/src/util/
H A Dregister_allocate.h66 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
H A Dregister_allocate.c171 * Set up conflicts between base_reg and it's two half registers reg0 and
172 * reg1, but take care to not add conflicts between reg0 and reg1.
179 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict()
181 ra_add_reg_conflict(regs, reg0, base_reg); in ra_add_transitive_reg_pair_conflict()
187 ra_add_reg_conflict(regs, reg0, conflict); in ra_add_transitive_reg_pair_conflict()
188 if (conflict != reg0) in ra_add_transitive_reg_pair_conflict()
178 ra_add_transitive_reg_pair_conflict(struct ra_regs *regs, unsigned int base_reg, unsigned int reg0, unsigned int reg1) ra_add_transitive_reg_pair_conflict() argument
/third_party/vixl/test/aarch64/
H A Dtest-utils-aarch64.cc270 bool Equal64(const Register& reg0, in Equal64() argument
274 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits()); in Equal64()
275 int64_t reference = core->xreg(reg0.GetCode()); in Equal64()
281 bool NotEqual64(const Register& reg0, in NotEqual64() argument
284 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits()); in NotEqual64()
285 int64_t expected = core->xreg(reg0.GetCode()); in NotEqual64()
/third_party/ffmpeg/libavcodec/x86/
H A Dhevc_mc.asm519 %define %%reg0 %5
524 %define %%reg0 m0
542 pmaddubsw %%reg0, %3 ;x1*c1+x2*c2
544 paddw %%reg0, %%reg2
551 pmaddwd %%reg0, %3
553 paddd %%reg0, %%reg2
563 psrad %%reg0, %1-8
565 packssdw %%reg0, %%reg1
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerX8664.cpp2168 void AssemblerX8664::arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1) {
2173 emitRexRB(Ty, reg0, reg1);
2178 emitRegisterOperand(gprEncoding(reg0), gprEncoding(reg1));
2230 void AssemblerX8664::cmp(Type Ty, GPRRegister reg0, GPRRegister reg1) {
2231 arith_int<7>(Ty, reg0, reg1);
3130 void AssemblerX8664::xchg(Type Ty, GPRRegister reg0, GPRRegister reg1) { in xchg() argument
3135 if (reg0 == RegX8664::Encoded_Reg_rax) { in xchg()
3139 emitRexB(Ty, reg0); in xchg()
3140 emitUint8(0x90 + gprEncoding(reg0)); in xchg()
3142 emitRexRB(Ty, reg0, reg in xchg()
[all...]
H A DIceAssemblerX8632.h716 void cmp(Type Ty, GPRRegister reg0, GPRRegister reg1);
722 void test(Type Ty, GPRRegister reg0, GPRRegister reg1);
860 void xchg(Type Ty, GPRRegister reg0, GPRRegister reg1);
923 void arith_int(Type Ty, GPRRegister reg0, GPRRegister reg1);
/third_party/node/deps/v8/src/codegen/s390/
H A Dassembler-s390.cc195 int16_t reg0; in ProbeImpl() local
202 : "=Q"(facilities), "=r"(reg0) in ProbeImpl()

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