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Searched refs:outputs_written (Results 1 - 25 of 84) sorted by relevance

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/third_party/mesa3d/src/panfrost/lib/
H A Dpan_shader.c235 s->info.outputs_written & (1 << VARYING_SLOT_PSIZ); in pan_shader_compile()
239 util_last_bit(s->info.outputs_written >> VARYING_SLOT_VAR0); in pan_shader_compile()
246 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) in pan_shader_compile()
248 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL)) in pan_shader_compile()
250 if (s->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)) in pan_shader_compile()
254 info->fs.outputs_written = s->info.outputs_written >> FRAG_RESULT_DATA0; in pan_shader_compile()
310 info->outputs_written = s->info.outputs_written; in pan_shader_compile()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_nir_lower_alpha_to_coverage.c86 const uint64_t outputs_written = shader->info.outputs_written; in brw_nir_lower_alpha_to_coverage() local
87 if (!(outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)) || in brw_nir_lower_alpha_to_coverage()
88 !(outputs_written & (BITFIELD64_BIT(FRAG_RESULT_COLOR) | in brw_nir_lower_alpha_to_coverage()
H A Dbrw_mesh.cpp362 uint64_t outputs_written = nir->info.outputs_written; in brw_compute_mue_map() local
365 if (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) & outputs_written) { in brw_compute_mue_map()
367 outputs_written &= ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT); in brw_compute_mue_map()
369 if (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) & outputs_written) { in brw_compute_mue_map()
371 outputs_written &= ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES); in brw_compute_mue_map()
381 (nir->info.outputs_written & (BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) | in brw_compute_mue_map()
389 u_foreach_bit64(location, outputs_written & nir->info.per_primitive_outputs) { in brw_compute_mue_map()
431 u_foreach_bit64(location, outputs_written & ~nir->info.per_primitive_outputs) { in brw_compute_mue_map()
H A Dbrw_vec4_tcs.cpp372 nir->info.outputs_written = key->outputs_written; in brw_compile_tcs()
379 nir->info.outputs_written, in brw_compile_tcs()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_info.c652 info->writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH); in si_nir_scan_shader()
653 info->writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL); in si_nir_scan_shader()
654 info->writes_samplemask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK); in si_nir_scan_shader()
656 info->colors_written = nir->info.outputs_written >> FRAG_RESULT_DATA0; in si_nir_scan_shader()
657 if (nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR)) { in si_nir_scan_shader()
664 info->writes_primid = nir->info.outputs_written & VARYING_BIT_PRIMITIVE_ID; in si_nir_scan_shader()
665 info->writes_viewport_index = nir->info.outputs_written & VARYING_BIT_VIEWPORT; in si_nir_scan_shader()
666 info->writes_layer = nir->info.outputs_written & VARYING_BIT_LAYER; in si_nir_scan_shader()
667 info->writes_psize = nir->info.outputs_written & VARYING_BIT_PSIZ; in si_nir_scan_shader()
668 info->writes_clipvertex = nir->info.outputs_written in si_nir_scan_shader()
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H A Dsi_nir_optim.c175 util_bitcount64(shader->info.outputs_written) != 1) in si_nir_is_output_const_if_tex_is_const()
/third_party/mesa3d/src/compiler/nir/
H A Dnir_lower_fragcolor.c82 b->shader->info.outputs_written &= ~BITFIELD64_BIT(FRAG_RESULT_COLOR); in lower_fragcolor_instr()
83 b->shader->info.outputs_written |= BITFIELD64_BIT(FRAG_RESULT_DATA0); in lower_fragcolor_instr()
94 b->shader->info.outputs_written |= BITFIELD64_BIT(FRAG_RESULT_DATA0 + i); in lower_fragcolor_instr()
H A Dnir_lower_passthrough_edgeflags.c47 util_bitcount64(shader->info.outputs_written)); in lower_impl()
88 shader->info.outputs_written |= VARYING_BIT_EDGE; in lower_impl()
H A Dnir_gather_info.c167 shader->info.outputs_written |= bitfield; in set_io_mask()
634 shader->info.outputs_written |= slot_mask; in gather_intrinsic_info()
949 shader->info.outputs_written = 0; in nir_shader_gather_info()
/third_party/mesa3d/src/mesa/program/
H A Darbprogparse.c109 program->info.outputs_written = prog.info.outputs_written; in _mesa_parse_arb_fragment_program()
196 program->info.outputs_written = prog.info.outputs_written; in _mesa_parse_arb_vertex_program()
H A Dprogramopt.c111 vprog->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_POS); in insert_mvp_dp4_code()
212 vprog->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_POS); in insert_mvp_mad_code()
267 if (!(fprog->info.outputs_written & (1 << FRAG_RESULT_COLOR))) { in _mesa_append_fog_code()
412 assert(fprog->info.outputs_written & (1 << FRAG_RESULT_COLOR)); in _mesa_append_fog_code()
H A Dprog_to_nir.c931 int max_outputs = util_last_bit64(c->prog->info.outputs_written); in setup_registers_and_variables()
934 uint64_t outputs_written = c->prog->info.outputs_written; in setup_registers_and_variables() local
935 while (outputs_written) { in setup_registers_and_variables()
936 const int i = u_bit_scan64(&outputs_written); in setup_registers_and_variables()
/third_party/mesa3d/src/mesa/state_tracker/
H A Dst_util.h81 if (vertProg->info.outputs_written & in st_point_size_per_vertex()
102 return !!(last->info.outputs_written & in st_point_size_per_vertex()
H A Dst_atom_shader.c222 (vp->info.outputs_written & in st_update_vp()
277 (prog->info.outputs_written & in st_update_common_program()
H A Dst_program.c443 if (prog->info.outputs_written & BITFIELD64_BIT(attr)) in st_prepare_vertex_program()
469 if (prog->info.outputs_written & BITFIELD64_BIT(attr)) in st_translate_stream_output_info()
640 if (nir->info.outputs_written & VARYING_BIT_CLIP_DIST0) in lower_ucp()
736 * update the inputs_read/outputs_written. However, with in st_create_common_variant()
738 * decided at link time with outputs_written updated so the two line in st_create_common_variant()
1232 if (nir->info.outputs_written & VARYING_BIT_PSIZ) in st_can_add_pointsize_to_program()
1271 (prog->info.outputs_written & (VARYING_SLOT_COL0 | in st_precompile_shader_variant()
/third_party/mesa3d/src/gallium/drivers/d3d12/
H A Dd3d12_compiler.cpp299 if (fs->initial->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR)) in frag_result_color_lowering()
360 (vs->initial->info.outputs_written & VARYING_BIT_EDGE || in fill_mode_lowered()
392 (gs->initial->info.outputs_written & VARYING_BIT_PSIZ || in needs_point_sprite_lowering()
403 vs->initial->info.outputs_written & VARYING_BIT_PSIZ)) && in needs_point_sprite_lowering()
404 (vs->initial->info.outputs_written & VARYING_BIT_POS)); in needs_point_sprite_lowering()
628 vs->initial->info.outputs_written, false); in validate_geometry_shader_variant()
658 vs->initial->info.outputs_written, false); in validate_tess_ctrl_shader_variant()
886 uint64_t mask = prev->current->nir->info.outputs_written & ~system_out_values; in d3d12_fill_shader_key()
889 key->prev_varying_outputs = prev->current->nir->info.outputs_written; in d3d12_fill_shader_key()
1204 uint64_t mask = key.required_varying_outputs.mask & ~new_nir_variant->info.outputs_written; in select_shader_variant()
1322 update_so_info(struct pipe_stream_output_info *so_info, uint64_t outputs_written) update_so_info() argument
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/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_program.c349 nir->info.outputs_written &= ~VARYING_BIT_EDGE; in crocus_fix_edge_flags()
371 * slots are assigned consecutively to all outputs in info->outputs_written.
382 uint64_t outputs_written) in update_so_info()
386 while (outputs_written) { in update_so_info()
387 reverse_map[slot++] = u_bit_scan64(&outputs_written); in update_so_info()
418 //info->outputs_written |= 1ull << output->register_index; in update_so_info()
1117 GLbitfield64 outputs_written = user_varyings; in crocus_vs_outputs_written() local
1122 outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE); in crocus_vs_outputs_written()
1132 outputs_written |= BITFIELD64_BIT(VARYING_SLOT_TEX0 + i); in crocus_vs_outputs_written()
1136 if (outputs_written in crocus_vs_outputs_written()
381 update_so_info(struct pipe_stream_output_info *so_info, uint64_t outputs_written) update_so_info() argument
1229 uint64_t outputs_written = crocus_compile_vs() local
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/third_party/mesa3d/src/gallium/auxiliary/nir/
H A Dnir_to_tgsi_info.c756 nir->info.outputs_written & (1ull << loc)) { in nir_tgsi_scan_shader()
763 uint64_t outputs_written = nir->info.outputs_written; in nir_tgsi_scan_shader() local
765 while (outputs_written) { in nir_tgsi_scan_shader()
766 unsigned location = u_bit_scan64(&outputs_written); in nir_tgsi_scan_shader()
767 unsigned i = util_bitcount64(nir->info.outputs_written & in nir_tgsi_scan_shader()
778 num_outputs = util_bitcount64(nir->info.outputs_written); in nir_tgsi_scan_shader()
/third_party/mesa3d/src/microsoft/spirv_to_dxil/
H A Ddxil_spirv_nir.c458 prev_stage_nir->info.outputs_written; in kill_undefined_varyings()
522 shader->info.outputs_written & ~next_stage_shader->info.inputs_read; in dxil_spirv_nir_kill_unused_outputs()
570 prev_stage_nir->info.outputs_written); in dxil_spirv_nir_link()
571 prev_stage_nir->info.outputs_written = in dxil_spirv_nir_link()
752 nir->info.outputs_written = in dxil_spirv_nir_passes()
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_program.c125 .outputs_written = key->outputs_written, in iris_to_brw_tcs_key()
379 nir->info.outputs_written &= ~VARYING_BIT_EDGE; in iris_fix_edge_flags()
401 * slots are assigned consecutively to all outputs in info->outputs_written.
412 uint64_t outputs_written) in update_so_info()
416 while (outputs_written) { in update_so_info()
417 reverse_map[slot++] = u_bit_scan64(&outputs_written); in update_so_info()
448 //info->outputs_written |= 1ull << output->register_index; in update_so_info()
1348 &vue_prog_data->vue_map, nir->info.outputs_written, in iris_compile_vs()
1476 *per_vertex_slots |= tcs->outputs_written; in get_unified_tess_slots()
411 update_so_info(struct pipe_stream_output_info *so_info, uint64_t outputs_written) update_so_info() argument
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/third_party/mesa3d/src/amd/vulkan/
H A Dradv_shader_info.c514 nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask; in radv_nir_shader_info_pass()
516 nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask; in radv_nir_shader_info_pass()
637 info->ps.writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH); in radv_nir_shader_info_pass()
638 info->ps.writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL); in radv_nir_shader_info_pass()
639 info->ps.writes_sample_mask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK); in radv_nir_shader_info_pass()
675 info->gs.gsvs_vertex_size = (util_bitcount64(nir->info.outputs_written) + add_clip) * 16; in radv_nir_shader_info_pass()
/third_party/mesa3d/src/compiler/glsl/
H A Dir_set_program_inouts.cpp27 * Sets the inputs_read and outputs_written of Mesa programs.
33 * provides support for setting inputs_read and outputs_written right
86 * inputs_read/outputs_written, everything but matrices uses one in mark()
89 * than inputs_read/outputs_written. in mark()
133 prog->info.outputs_written |= bitfield; in mark()
430 prog->info.outputs_written = 0; in do_set_program_inouts()
/third_party/mesa3d/src/panfrost/util/
H A Dpan_ir.h296 BITSET_WORD outputs_written; member
352 uint64_t outputs_written; member
/third_party/mesa3d/src/gallium/drivers/panfrost/
H A Dpan_context.c321 (so->nir->info.outputs_written & BITFIELD_MASK(VARYING_SLOT_VAR0)) & in panfrost_create_shader_state()
437 * slots are assigned consecutively to all outputs in info->outputs_written.
450 uint64_t outputs_written) in update_so_info()
456 while (outputs_written) in update_so_info()
457 reverse_map[slot++] = u_bit_scan64(&outputs_written); in update_so_info()
511 shader_state->info.outputs_written); in panfrost_new_variant_locked()
449 update_so_info(struct pipe_stream_output_info *so_info, uint64_t outputs_written) update_so_info() argument
/third_party/mesa3d/src/compiler/
H A Dshader_info.h163 uint64_t outputs_written; member

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