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Searched refs:num_vgprs (Results 1 - 19 of 19) sorted by relevance

/third_party/mesa3d/src/amd/common/
H A Dac_binary.c54 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 8); in ac_parse_shader_binary_config()
56 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4); in ac_parse_shader_binary_config()
129 * For shader-db stats, set num_vgprs that the hw actually uses. in ac_parse_shader_binary_config()
132 conf->num_vgprs = align(conf->num_vgprs, wave_size == 32 ? 16 : 8); in ac_parse_shader_binary_config()
H A Dac_binary.h39 unsigned num_vgprs; member
H A Dac_rtld.c537 config->num_vgprs = MAX2(config->num_vgprs, c.num_vgprs); in ac_rtld_read_config()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader.c617 unsigned num_user_sgprs, num_vgprs; in si_init_shader_args() local
639 num_vgprs = ngg_cull_shader ? 9 : 5; in si_init_shader_args()
644 for (i = 0; i < num_vgprs; i++) in si_init_shader_args()
1059 if (conf->num_vgprs) { in si_calculate_max_simd_waves()
1063 max_simd_waves = MIN2(max_simd_waves, max_vgprs / conf->num_vgprs); in si_calculate_max_simd_waves()
1088 conf->num_sgprs, conf->num_vgprs, si_get_shader_binary_size(screen, shader), in si_shader_dump_stats_for_shader_db()
1123 conf->num_sgprs, conf->num_vgprs, conf->spilled_sgprs, conf->spilled_vgprs, in si_shader_dump_stats()
1939 if (shader->config.num_sgprs > max_sgprs || shader->config.num_vgprs > max_vgprs) { in si_compile_shader()
1943 shader->config.num_sgprs, shader->config.num_vgprs, max_sgprs, max_vgprs); in si_compile_shader()
2524 shader->config.num_vgprs in si_create_shader_variant()
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H A Dsi_shader_llvm.c438 unsigned num_sgprs, num_vgprs; in si_build_wrapper_function() local
454 num_vgprs = 0; in si_build_wrapper_function()
463 assert(num_vgprs == 0); in si_build_wrapper_function()
466 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4; in si_build_wrapper_function()
471 while (gprs < num_sgprs + num_vgprs) { in si_build_wrapper_function()
501 assert(gprs + size <= num_sgprs + num_vgprs && in si_build_wrapper_function()
H A Dsi_state_shaders.cpp697 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_ls()
751 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) | in si_shader_hs()
820 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_es()
1106 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) | in si_shader_gs()
1154 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | in si_shader_gs()
1422 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) |
1736 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) |
2011 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (shader->wave_size == 32 ? 8 : 4)) |
H A Dsi_compute.c100 out_config->num_vgprs = code_object->workitem_vgpr_count; in code_object_to_config()
198 shader->config.rsrc1 = S_00B848_VGPRS((shader->config.num_vgprs - 1) / in si_create_compute_state_async()
H A Dgfx10_shader_ngg.c1490 unsigned num_vgprs = uses_tes_prim_id ? 4 : 3; in gfx10_ngg_culling_build_end() local
1491 for (unsigned i = 0; i < num_vgprs; i++) { in gfx10_ngg_culling_build_end()
1495 if (num_vgprs == 3) in gfx10_ngg_culling_build_end()
H A Dsi_sqtt.c1060 record->shader_data[gl_shader_stage].vgpr_count = shader->config.num_vgprs; in si_sqtt_add_code_object()
/third_party/mesa3d/src/amd/compiler/
H A Daco_interface.h63 uint32_t num_vgprs,
H A Daco_interface.cpp313 config.num_vgprs, in aco_compile_vs_prolog()
358 config.num_vgprs, in aco_compile_ps_epilog()
H A Daco_validate.cpp1027 op.physReg().reg_b + op.bytes() > (256 + program->config->num_vgprs) * 4) || in validate_ra()
1058 def.physReg().reg_b + def.bytes() > (256 + program->config->num_vgprs) * 4) || in validate_ra()
H A Daco_lower_to_hw_instr.cpp854 unsigned shared_vgpr_reg_0 = align(program->config->num_vgprs, 4) + 256; in emit_gfx10_wave64_bpermute()
H A Daco_register_allocation.cpp3086 program->config->num_vgprs = get_vgpr_alloc(program, ctx.max_used_vgpr + 1); in register_allocation()
H A Daco_instruction_selection.cpp12362 unsigned num_vgprs = attributes_start.reg() - 256;
12363 num_vgprs += key->num_attributes * 4;
12365 num_vgprs++; /* make space for nontrivial_tmp_vgpr1 */
12522 program->config->num_vgprs = get_vgpr_alloc(program, num_vgprs);
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_shader.c1659 unsigned num_vgprs = MAX2(config_in->num_vgprs, num_input_vgprs); in radv_postprocess_config() local
1670 config_out->num_vgprs = num_vgprs; in radv_postprocess_config()
1691 config_out->rsrc1 = S_00B848_VGPRS((num_vgprs - 1) / (info->wave_size == 32 ? 8 : 4)) | in radv_postprocess_config()
2387 shader_part->rsrc1 = S_00B848_VGPRS((bin->num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) |
2397 uint32_t num_vgprs,
2411 part_binary->num_vgprs = num_vgprs;
2670 if (conf->num_vgprs) {
2395 radv_aco_build_shader_part(void **bin, uint32_t num_sgprs, uint32_t num_vgprs, uint32_t num_preserved_sgprs, const uint32_t *code, uint32_t code_size, const char *disasm_str, uint32_t disasm_size) global() argument
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H A Dradv_shader.h461 uint8_t num_vgprs; member
H A Dradv_pipeline.c7534 s->value.u64 = shader->config.num_vgprs; in radv_GetPipelineExecutableStatisticsKHR()
/third_party/mesa3d/src/amd/vulkan/layers/
H A Dradv_sqtt_layer.c903 record->shader_data[i].vgpr_count = shader->config.num_vgprs; in radv_add_code_object()

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