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Searched refs:movn (Results 1 - 25 of 26) sorted by relevance

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/third_party/rust/crates/rustix/src/backend/linux_raw/arch/outline/
H A Dmips.s33 movn $2, $8, $7
55 movn $2, $8, $7
97 movn $2, $8, $7
119 movn $2, $8, $7
141 movn $2, $8, $7
163 movn $2, $8, $7
185 movn $2, $8, $7
209 movn $2, $8, $7
H A Dmips64.s33 movn $2, $12, $7
55 movn $2, $12, $7
97 movn $2, $12, $7
119 movn $2, $12, $7
141 movn $2, $12, $7
163 movn $2, $12, $7
185 movn $2, $12, $7
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.h219 void movn(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
H A DIceInstMIPS32.cpp883 Asm->movn(getDest(), getSrc(0), getSrc(1)); in emitIAS()
H A DIceAssemblerMIPS32.cpp854 void AssemblerMIPS32::movn(const Operand *OpRd, const Operand *OpRs, in movn() function in Ice::MIPS32::AssemblerMIPS32
857 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn"); in movn()
863 emitCOP1FmtRtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "movn.d"); in movn_d()
869 emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s"); in movn_s()
/third_party/node/deps/v8/src/diagnostics/mips/
H A Ddisasm-mips.cc1007 Format(instr, "movn.'t 'fd, 'fs, 'rt"); in DecodeTypeRegisterRsType()
1410 Format(instr, "movn 'rd, 'rs, 'rt"); in DecodeTypeRegisterSPECIAL()
/third_party/vixl/test/aarch64/
H A Dtest-disasm-aarch64.cc129 COMPARE(movn(w14, 0x1234), "mov w14, #0xffffedcb"); in TEST()
130 COMPARE(movn(x15, 0xabcd0000), "mov x15, #0xffffffff5432ffff"); in TEST()
131 COMPARE(movn(x16, 0x555500000000), "mov x16, #0xffffaaaaffffffff"); in TEST()
132 COMPARE(movn(x17, 0xaaaa000000000000), "mov x17, #0x5555ffffffffffff"); in TEST()
133 COMPARE(movn(w18, 0xabcd, 16), "mov w18, #0x5432ffff"); in TEST()
134 COMPARE(movn(x19, 0x5555, 32), "mov x19, #0xffffaaaaffffffff"); in TEST()
135 COMPARE(movn(x20, 0xaaaa, 48), "mov x20, #0x5555ffffffffffff"); in TEST()
153 COMPARE(movn(x27, 0, 48), "movn x27, #0x0"); in TEST()
154 COMPARE(movn(w2 in TEST()
[all...]
H A Dtest-trace-aarch64.cc246 __ movn(w17, 132); in GenerateTestSequenceBase()
247 __ movn(x18, 133); in GenerateTestSequenceBase()
H A Dtest-cpu-features-aarch64.cc371 TEST_NONE(movn_0, movn(w0, UINT32_C(0xbd2f)))
372 TEST_NONE(movn_1, movn(x0, UINT64_C(0x560c) << 16))
/third_party/node/deps/v8/src/diagnostics/mips64/
H A Ddisasm-mips64.cc1067 Format(instr, "movn.'t 'fd, 'fs, 'rt"); in DecodeTypeRegisterRsType()
1642 Format(instr, "movn 'rd, 'rs, 'rt"); in DecodeTypeRegisterSPECIAL()
/third_party/node/deps/v8/src/codegen/mips/
H A Dmacro-assembler-mips.cc1520 movn(dst_high, dst_low, scratch1); in CallRecordWriteStub()
1521 movn(dst_low, zero_reg, scratch1); in CallRecordWriteStub()
1577 movn(dst_low, dst_high, scratch1); in CallRecordWriteStub()
1578 movn(dst_high, zero_reg, scratch1); in CallRecordWriteStub()
2509 movn(rd, rs, rt); in CallRecordWriteStub()
H A Dassembler-mips.h598 void movn(Register rd, Register rs, Register rt);
H A Dassembler-mips.cc2317 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() function in v8::internal::Assembler
/third_party/node/deps/v8/src/codegen/arm64/
H A Dmacro-assembler-arm64.cc275 // 2. 32-bit move inverted (movn). in Mov()
309 // Iterate through the halfwords. Use movn/movz for the first non-ignored in Mov()
318 movn(temp, (~imm16) & 0xFFFFL, 16 * i); in Mov()
625 // The movn instruction can generate immediates containing an arbitrary 16-bit
705 movn(dst, dst.Is64Bits() ? ~imm : (~imm & kWRegMask)); in TryOneInstrMoveImmediate()
743 // different immediate that may be encodable using movn or orr-immediate. in MoveImmediateForShiftedOp()
H A Dassembler-arm64.h898 void movn(const Register& rd, uint64_t imm, int shift = -1) {
/third_party/node/deps/v8/src/codegen/mips64/
H A Dassembler-mips64.h642 void movn(Register rd, Register rs, Register rt);
H A Dmacro-assembler-mips64.cc3028 movn(rd, rs, rt); in CallRecordWriteStub()
H A Dassembler-mips64.cc2456 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() function in v8::internal::Assembler
/third_party/vixl/src/aarch64/
H A Dmacro-assembler-aarch64.cc504 // 2. 32-bit move inverted (movn). in Emit()
546 // Iterate through the halfwords. Use movn/movz for the first non-ignored in Emit()
555 if (emit_code) masm->movn(temp, ~imm16 & 0xffff, 16 * i); in Emit()
H A Dassembler-aarch64.h2125 void movn(const Register& rd, uint64_t imm, int shift = -1) {
2134 // Move immediate, aliases for movz, movn, orr.
4051 // As for movz/movk/movn, if the default shift of -1 is specified to dup, the
H A Dassembler-aarch64.cc5907 assm->movn(dst, dst.Is64Bits() ? ~imm : (~imm & kWRegMask));
6493 // The movn instruction can generate immediates containing an arbitrary 16-bit
/third_party/node/deps/v8/src/builtins/mips/
H A Dbuiltins-mips.cc835 __ movn(params_size, actual_params_size, t2); in LeaveInterpreterFrame()
/third_party/node/deps/v8/src/builtins/mips64/
H A Dbuiltins-mips64.cc845 __ movn(params_size, actual_params_size, t2); in LeaveInterpreterFrame()
/third_party/node/deps/v8/src/compiler/backend/mips64/
H A Dcode-generator-mips64.cc4346 __ movn(t0, kScratchReg, kScratchReg2); in AssembleConstructFrame()
/third_party/node/deps/v8/src/compiler/backend/mips/
H A Dcode-generator-mips.cc4142 __ movn(t0, kScratchReg, kScratchReg2); in AssembleConstructFrame()

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