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/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/aes/
H A Daes-mips.S153 lwr $12,3($1) # Te1[s1>>16]
155 lwr $13,3($2) # Te1[s2>>16]
157 lwr $14,3($24) # Te1[s3>>16]
159 lwr $15,3($25) # Te1[s0>>16]
239 lwr $16,2($1) # Te2[s2>>8]
241 lwr $17,2($2) # Te2[s3>>8]
243 lwr $18,2($24) # Te2[s0>>8]
245 lwr $19,2($25) # Te2[s1>>8]
260 lwr $20,1($1) # Te3[s3]
262 lwr
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/aes/
H A Daes-mips.S153 lwr $12,3($1) # Te1[s1>>16]
155 lwr $13,3($2) # Te1[s2>>16]
157 lwr $14,3($24) # Te1[s3>>16]
159 lwr $15,3($25) # Te1[s0>>16]
239 lwr $16,2($1) # Te2[s2>>8]
241 lwr $17,2($2) # Te2[s3>>8]
243 lwr $18,2($24) # Te2[s0>>8]
245 lwr $19,2($25) # Te2[s1>>8]
260 lwr $20,1($1) # Te3[s3]
262 lwr
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/sha/
H A Dsha1-mips.S44 lwr $8,0($5)
71 lwr $9,1*4+0($5)
81 lwr $9,1*4+0($5)
118 lwr $10,2*4+0($5)
128 lwr $10,2*4+0($5)
165 lwr $11,3*4+0($5)
175 lwr $11,3*4+0($5)
212 lwr $12,4*4+0($5)
222 lwr $12,4*4+0($5)
259 lwr
[all...]
H A Dsha256-mips.S52 lwr $8,0($5)
58 lwr $9,4($5)
140 lwr $10,8($5)
222 lwr $11,12($5)
304 lwr $12,16($5)
386 lwr $13,20($5)
468 lwr $14,24($5)
550 lwr $15,28($5)
632 lwr $16,32($5)
714 lwr
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/sha/
H A Dsha1-mips.S44 lwr $8,0($5)
71 lwr $9,1*4+0($5)
81 lwr $9,1*4+0($5)
118 lwr $10,2*4+0($5)
128 lwr $10,2*4+0($5)
165 lwr $11,3*4+0($5)
175 lwr $11,3*4+0($5)
212 lwr $12,4*4+0($5)
222 lwr $12,4*4+0($5)
259 lwr
[all...]
H A Dsha256-mips.S52 lwr $8,0($5)
58 lwr $9,4($5)
140 lwr $10,8($5)
222 lwr $11,12($5)
304 lwr $12,16($5)
386 lwr $13,20($5)
468 lwr $14,24($5)
550 lwr $15,28($5)
632 lwr $16,32($5)
714 lwr
[all...]
/third_party/node/deps/openssl/openssl/crypto/aes/asm/
H A Daes-mips.pl25 # additional rotations. Rotations are implemented with lwl/lwr pairs,
277 lwr $t0,2($i0) # Te1[s1>>16]
279 lwr $t1,2($i1) # Te1[s2>>16]
281 lwr $t2,2($i2) # Te1[s3>>16]
283 lwr $t3,2($i3) # Te1[s0>>16]
363 lwr $t4,1($i0) # Te2[s2>>8]
365 lwr $t5,1($i1) # Te2[s3>>8]
367 lwr $t6,1($i2) # Te2[s0>>8]
369 lwr $t7,1($i3) # Te2[s1>>8]
384 lwr
[all...]
/third_party/openssl/crypto/aes/asm/
H A Daes-mips.pl25 # additional rotations. Rotations are implemented with lwl/lwr pairs,
277 lwr $t0,2($i0) # Te1[s1>>16]
279 lwr $t1,2($i1) # Te1[s2>>16]
281 lwr $t2,2($i2) # Te1[s3>>16]
283 lwr $t3,2($i3) # Te1[s0>>16]
363 lwr $t4,1($i0) # Te2[s2>>8]
365 lwr $t5,1($i1) # Te2[s3>>8]
367 lwr $t6,1($i2) # Te2[s0>>8]
369 lwr $t7,1($i3) # Te2[s1>>8]
384 lwr
[all...]
/third_party/node/deps/v8/src/builtins/mips/
H A Dbuiltins-mips.cc3368 __ lwr(t8, MemOperand(a1)); in Generate_MemCopyUint8Uint8()
3530 __ lwr(v1, MemOperand(a1)); in Generate_MemCopyUint8Uint8()
3538 __ lwr(v1, in Generate_MemCopyUint8Uint8()
3573 __ lwr(t0, MemOperand(a1)); in Generate_MemCopyUint8Uint8()
3574 __ lwr(t1, MemOperand(a1, 1, loadstore_chunk)); in Generate_MemCopyUint8Uint8()
3575 __ lwr(t2, MemOperand(a1, 2, loadstore_chunk)); in Generate_MemCopyUint8Uint8()
3581 __ lwr(t3, MemOperand(a1, 3, loadstore_chunk)); // Maybe in delay slot. in Generate_MemCopyUint8Uint8()
3587 __ lwr(t4, MemOperand(a1, 4, loadstore_chunk)); in Generate_MemCopyUint8Uint8()
3588 __ lwr(t5, MemOperand(a1, 5, loadstore_chunk)); in Generate_MemCopyUint8Uint8()
3589 __ lwr(t in Generate_MemCopyUint8Uint8()
[all...]
/third_party/node/deps/openssl/openssl/crypto/sha/asm/
H A Dsha1-mips.pl20 # to deploy lwl/lwr pair to load unaligned input. One could have
138 lwr @X[$j],$j*4+$LSB($inp)
148 lwr @X[$j],$j*4+$LSB($inp)
398 lwr @X[0],$LSB($inp)
/third_party/openssl/crypto/sha/asm/
H A Dsha1-mips.pl20 # to deploy lwl/lwr pair to load unaligned input. One could have
138 lwr @X[$j],$j*4+$LSB($inp)
148 lwr @X[$j],$j*4+$LSB($inp)
398 lwr @X[0],$LSB($inp)
/third_party/node/deps/v8/src/diagnostics/mips64/
H A Ddisasm-mips64.cc2142 Format(instr, "lwr 'rt, 'imm16s('rs)"); in DecodeTypeImmediate()
/third_party/node/deps/v8/src/codegen/mips64/
H A Dassembler-mips64.h582 void lwr(Register rd, const MemOperand& rs);
H A Dmacro-assembler-mips64.cc1137 lwr(rd, MemOperand(source.rm(), source.offset() + kMipsLwrOffset)); in CallRecordWriteStub()
1142 lwr(scratch, MemOperand(rs.rm(), rs.offset() + kMipsLwrOffset)); in CallRecordWriteStub()
H A Dassembler-mips64.cc2176 void Assembler::lwr(Register rd, const MemOperand& rs) { in lwr() function in v8::internal::Assembler
/third_party/node/deps/v8/src/codegen/mips/
H A Dassembler-mips.h546 void lwr(Register rd, const MemOperand& rs);
H A Dmacro-assembler-mips.cc1034 lwr(rd, MemOperand(source.rm(), source.offset() + kMipsLwrOffset)); in CallRecordWriteStub()
1039 lwr(scratch, MemOperand(rs.rm(), rs.offset() + kMipsLwrOffset)); in CallRecordWriteStub()
H A Dassembler-mips.cc2095 void Assembler::lwr(Register rd, const MemOperand& rs) { in lwr() function in v8::internal::Assembler
/third_party/sqlite/src/
H A Dsqlite3.c74269 int lwr, upr, idx, c; global() local
74513 int lwr, upr, idx, c; global() local
134522 int upr, lwr, mid = 0, rc; global() local
[all...]

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