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Searched refs:lwl (Results 1 - 17 of 17) sorted by relevance

/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/aes/
H A Daes-mips.S149 lwl $12,2($1) # Te1[s1>>16]
150 lwl $13,2($2) # Te1[s2>>16]
151 lwl $14,2($24) # Te1[s3>>16]
152 lwl $15,2($25) # Te1[s0>>16]
235 lwl $16,1($1) # Te2[s2>>8]
236 lwl $17,1($2) # Te2[s3>>8]
237 lwl $18,1($24) # Te2[s0>>8]
238 lwl $19,1($25) # Te2[s1>>8]
256 lwl $20,0($1) # Te3[s3]
257 lwl
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/aes/
H A Daes-mips.S149 lwl $12,2($1) # Te1[s1>>16]
150 lwl $13,2($2) # Te1[s2>>16]
151 lwl $14,2($24) # Te1[s3>>16]
152 lwl $15,2($25) # Te1[s0>>16]
235 lwl $16,1($1) # Te2[s2>>8]
236 lwl $17,1($2) # Te2[s3>>8]
237 lwl $18,1($24) # Te2[s0>>8]
238 lwl $19,1($25) # Te2[s1>>8]
256 lwl $20,0($1) # Te3[s3]
257 lwl
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/sha/
H A Dsha1-mips.S42 lwl $8,3($5)
70 lwl $9,1*4+3($5)
78 lwl $9,1*4+3($5)
117 lwl $10,2*4+3($5)
125 lwl $10,2*4+3($5)
164 lwl $11,3*4+3($5)
172 lwl $11,3*4+3($5)
211 lwl $12,4*4+3($5)
219 lwl $12,4*4+3($5)
258 lwl
[all...]
H A Dsha256-mips.S51 lwl $8,3($5)
57 lwl $9,7($5)
139 lwl $10,11($5)
221 lwl $11,15($5)
303 lwl $12,19($5)
385 lwl $13,23($5)
467 lwl $14,27($5)
549 lwl $15,31($5)
631 lwl $16,35($5)
713 lwl
[all...]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/sha/
H A Dsha1-mips.S42 lwl $8,3($5)
70 lwl $9,1*4+3($5)
78 lwl $9,1*4+3($5)
117 lwl $10,2*4+3($5)
125 lwl $10,2*4+3($5)
164 lwl $11,3*4+3($5)
172 lwl $11,3*4+3($5)
211 lwl $12,4*4+3($5)
219 lwl $12,4*4+3($5)
258 lwl
[all...]
H A Dsha256-mips.S51 lwl $8,3($5)
57 lwl $9,7($5)
139 lwl $10,11($5)
221 lwl $11,15($5)
303 lwl $12,19($5)
385 lwl $13,23($5)
467 lwl $14,27($5)
549 lwl $15,31($5)
631 lwl $16,35($5)
713 lwl
[all...]
/third_party/node/deps/openssl/openssl/crypto/aes/asm/
H A Daes-mips.pl25 # additional rotations. Rotations are implemented with lwl/lwr pairs,
273 lwl $t0,3($i0) # Te1[s1>>16]
274 lwl $t1,3($i1) # Te1[s2>>16]
275 lwl $t2,3($i2) # Te1[s3>>16]
276 lwl $t3,3($i3) # Te1[s0>>16]
359 lwl $t4,2($i0) # Te2[s2>>8]
360 lwl $t5,2($i1) # Te2[s3>>8]
361 lwl $t6,2($i2) # Te2[s0>>8]
362 lwl $t7,2($i3) # Te2[s1>>8]
380 lwl
[all...]
/third_party/openssl/crypto/aes/asm/
H A Daes-mips.pl25 # additional rotations. Rotations are implemented with lwl/lwr pairs,
273 lwl $t0,3($i0) # Te1[s1>>16]
274 lwl $t1,3($i1) # Te1[s2>>16]
275 lwl $t2,3($i2) # Te1[s3>>16]
276 lwl $t3,3($i3) # Te1[s0>>16]
359 lwl $t4,2($i0) # Te2[s2>>8]
360 lwl $t5,2($i1) # Te2[s3>>8]
361 lwl $t6,2($i2) # Te2[s0>>8]
362 lwl $t7,2($i3) # Te2[s1>>8]
380 lwl
[all...]
/third_party/node/deps/v8/src/builtins/mips/
H A Dbuiltins-mips.cc3373 __ lwl(t8, MemOperand(a1)); in Generate_MemCopyUint8Uint8()
3531 __ lwl(v1, in Generate_MemCopyUint8Uint8()
3537 __ lwl(v1, MemOperand(a1)); in Generate_MemCopyUint8Uint8()
3591 __ lwl(t0, in Generate_MemCopyUint8Uint8()
3593 __ lwl(t1, in Generate_MemCopyUint8Uint8()
3595 __ lwl(t2, in Generate_MemCopyUint8Uint8()
3597 __ lwl(t3, in Generate_MemCopyUint8Uint8()
3599 __ lwl(t4, in Generate_MemCopyUint8Uint8()
3601 __ lwl(t5, in Generate_MemCopyUint8Uint8()
3603 __ lwl(t in Generate_MemCopyUint8Uint8()
[all...]
/third_party/node/deps/openssl/openssl/crypto/sha/asm/
H A Dsha1-mips.pl20 # to deploy lwl/lwr pair to load unaligned input. One could have
137 lwl @X[$j],$j*4+$MSB($inp)
145 lwl @X[$j],$j*4+$MSB($inp)
396 lwl @X[0],$MSB($inp)
/third_party/openssl/crypto/sha/asm/
H A Dsha1-mips.pl20 # to deploy lwl/lwr pair to load unaligned input. One could have
137 lwl @X[$j],$j*4+$MSB($inp)
145 lwl @X[$j],$j*4+$MSB($inp)
396 lwl @X[0],$MSB($inp)
/third_party/node/deps/v8/src/codegen/mips64/
H A Dassembler-mips64.h581 void lwl(Register rd, const MemOperand& rs);
H A Dmacro-assembler-mips64.cc1138 lwl(rd, MemOperand(source.rm(), source.offset() + kMipsLwlOffset)); in CallRecordWriteStub()
1143 lwl(scratch, MemOperand(rs.rm(), rs.offset() + kMipsLwlOffset)); in CallRecordWriteStub()
H A Dassembler-mips64.cc2170 void Assembler::lwl(Register rd, const MemOperand& rs) { in lwl() function in v8::internal::Assembler
/third_party/node/deps/v8/src/codegen/mips/
H A Dassembler-mips.h545 void lwl(Register rd, const MemOperand& rs);
H A Dmacro-assembler-mips.cc1035 lwl(rd, MemOperand(source.rm(), source.offset() + kMipsLwlOffset)); in CallRecordWriteStub()
1040 lwl(scratch, MemOperand(rs.rm(), rs.offset() + kMipsLwlOffset)); in CallRecordWriteStub()
H A Dassembler-mips.cc2088 void Assembler::lwl(Register rd, const MemOperand& rs) { in lwl() function in v8::internal::Assembler

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