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Searched refs:lri (Results 1 - 9 of 9) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/vc4/kernel/
H A Dvc4_validate_shaders.c130 static bool live_reg_is_upper_half(uint32_t lri) in live_reg_is_upper_half() argument
132 return (lri >=16 && lri < 32) || in live_reg_is_upper_half()
133 (lri >=32 + 16 && lri < 32 + 32); in live_reg_is_upper_half()
387 u32 lri = waddr_to_live_reg_index(waddr, is_b); in check_reg_write() local
389 if (lri != -1) { in check_reg_write()
397 validation_state->live_immediates[lri] = in check_reg_write()
400 validation_state->live_immediates[lri] = ~0; in check_reg_write()
403 if (live_reg_is_upper_half(lri)) in check_reg_write()
[all...]
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_genx_macros.h125 iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
126 lri.RegisterOffset = __genxml_reg_num(reg); \
127 lri.DataDWord = _dw[i]; \
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_genx_macros.h130 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
131 lri.RegisterOffset = __genxml_reg_num(reg); \
132 lri.DataDWord = _dw[i]; \
H A Dcrocus_state.c522 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in _crocus_emit_lri()
523 lri.RegisterOffset = reg; in _crocus_emit_lri()
524 lri.DataDWord = val; in _crocus_emit_lri()
7978 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
7979 lri.RegisterOffset = _3DPRIM_BASE_VERTEX;
7980 lri.DataDWord = 0;
/third_party/mesa3d/src/intel/vulkan/
H A DgenX_state.c385 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in init_render_queue_state()
386 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num); in init_render_queue_state()
387 lri.DataDWord = aux_base_addr & 0xffffffff; in init_render_queue_state()
389 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in init_render_queue_state()
390 lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4; in init_render_queue_state()
391 lri.DataDWord = aux_base_addr >> 32; in init_render_queue_state()
H A Dgfx8_cmd_buffer.c72 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in cmd_buffer_enable_pma_fix()
73 lri.RegisterOffset = GENX(CACHE_MODE_0_num); in cmd_buffer_enable_pma_fix()
74 lri.DataDWord = cache_mode; in cmd_buffer_enable_pma_fix()
85 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in cmd_buffer_enable_pma_fix()
86 lri.RegisterOffset = GENX(CACHE_MODE_1_num); in cmd_buffer_enable_pma_fix()
87 lri.DataDWord = cache_mode; in cmd_buffer_enable_pma_fix()
H A Danv_private.h1701 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { \
1702 lri.RegisterOffset = __anv_reg_num(reg); \
1703 lri.DataDWord = _dw[i]; \
H A DgenX_cmd_buffer.c2312 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in emit_apply_pipe_flushes()
2313 lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num); in emit_apply_pipe_flushes()
2314 lri.DataDWord = 1; in emit_apply_pipe_flushes()
4972 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in CmdBeginTransformFeedbackEXT()
4973 lri.RegisterOffset = GENX(SO_WRITE_OFFSET0_num) + idx * 4; in CmdBeginTransformFeedbackEXT()
4974 lri.DataDWord = 0; in CmdBeginTransformFeedbackEXT()
/third_party/mesa3d/src/intel/common/
H A Dmi_builder.h388 mi_builder_pack(b, GENX(MI_LOAD_REGISTER_IMM), dw, lri) { in _mi_copy_no_unref()
389 lri.DWordLength = GENX(MI_LOAD_REGISTER_IMM_length) + 2 - in _mi_copy_no_unref()
392 lri.AddCSMMIOStartOffset = reg.cs; in _mi_copy_no_unref()
490 mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) { in _mi_copy_no_unref()
492 lri.RegisterOffset = reg.num; in _mi_copy_no_unref()
494 lri.AddCSMMIOStartOffset = reg.cs; in _mi_copy_no_unref()
496 lri.DataDWord = src.imm; in _mi_copy_no_unref()

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