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/third_party/mesa3d/src/panfrost/bifrost/
H A Dbi_lower_divergent_indirects.c90 unsigned *lanes = data; in bi_lower_divergent_indirects_impl() local
100 for (unsigned i = 0; i < (*lanes); ++i) { in bi_lower_divergent_indirects_impl()
123 bi_lower_divergent_indirects(nir_shader *shader, unsigned lanes) in bi_lower_divergent_indirects() argument
127 nir_metadata_none, &lanes); in bi_lower_divergent_indirects()
H A Dcompiler.h46 * 8-bit lanes with two channels, use replicated forms for replicated forms
47 * (TODO: what about others?). For 8-bit lanes with four channels using
70 BI_SWIZZLE_B0022 = 12, /* for b02 lanes */
1396 bool bi_lower_divergent_indirects(nir_shader *shader, unsigned lanes);
/third_party/mesa3d/src/panfrost/bifrost/valhall/
H A Dvalhall.py103 halfswizzle = False, widen = False, lanes = False, combine = False, lane = None, absneg = False, notted = False, name = ""):
112 self.lanes = lanes
127 if widen or lanes or halfswizzle:
162 self.lanes = False
203 if len(srcs) == 3 and (srcs[1].widen or srcs[1].lanes):
238 lanes = el.get('lanes', False),
H A Dva_lower_constants.c146 if (!staging && (info.widen || info.lanes) && in va_resolve_constant()
210 } else if (info.size == VA_SIZE_8 && info.lanes) { in va_lower_constants()
H A Dvalhall.h80 bool lanes : 1; member
H A Dasm.py240 elif mod in enums[f'swizzles_{src.size}_bit'].bare_values and (src.widen or src.lanes):
274 die_if(not src.lanes, "Instruction doesn't take a lane")
H A Dva_pack.c501 } else if (src_info.lanes) { in va_pack_alu()
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_lowering_gm107.cpp151 // mov coordinates from lane l to all lanes in handleManualTXD()
156 // add dPdx from lane l to lanes dx in handleManualTXD()
161 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
164 // add dPdy from lane l to lanes dy in handleManualTXD()
169 add->lanes = 1; /* abused for .ndv */ in handleManualTXD()
197 // broadcast results from lane 0 to all lanes in handleManualTXD()
209 mov->lanes = 1 << l; in handleManualTXD()
248 insn->lanes = 0; /* abused for !.ndv */ in handleDFDX()
H A Dnv50_ir_emit_nv50.cpp631 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
651 code[1] = 0x00200000 | (i->lanes << 14); in emitLOAD()
798 code[1] |= (i->lanes << 14); in emitMOV()
2112 emitQUADOP(insn, insn->lanes, insn->subOp); in emitInstruction()
2187 if (i->join || i->lanes != 0xf || i->exit) in getMinEncodingSize()
H A Dnv50_ir.cpp581 lanes = 0xf; in init()
767 i->lanes = lanes; in clone()
H A Dnv50_ir_emit_gk110.cpp2365 code[0] = 0x00000002 | (i->lanes << 14); in emitMOV()
2379 code[1] |= i->lanes << 10; in emitMOV()
2692 emitQUADOP(insn, insn->subOp, insn->lanes); in emitInstruction()
H A Dnv50_ir_build_util.cpp270 quadop->lanes = l; in mkQuadop()
H A Dnv50_ir_emit_gv100.cpp306 emitField(72, 4, insn->lanes); in emitMOV()
582 emitField(77, 1, insn->lanes); /* abused for .ndv */ in emitFSWZADD()
H A Dnv50_ir_emit_nvc0.cpp2068 opc |= i->lanes << 5;
2886 emitQUADOP(insn, insn->subOp, insn->lanes);
2979 if (i->op == OP_MOV && i->lanes != 0xf) {
/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h342 // described. They do not consider the number of lanes that make up a vector.
345 // Check the number of lanes, ie. the format of the vector, using methods such
587 explicit VRegister(int code, int size_in_bits = kQRegSize, int lanes = 1)
591 EncodeLaneSizeInBits(size_in_bits, lanes)) {
621 static EncodedSize EncodeLaneSizeInBits(int size_in_bits, int lanes) {
622 VIXL_ASSERT(lanes >= 1);
623 VIXL_ASSERT((size_in_bits % lanes) == 0);
624 return EncodeSizeInBits(size_in_bits / lanes);
H A Dlogic-aarch64.cc1195 unsigned lanes = LaneCountFromFormat(vform); in sminmaxp() local
1199 for (unsigned i = 0; i < lanes; i += 2) { in sminmaxp()
1208 VIXL_ASSERT(((i >> 1) + (j * lanes / 2)) < ArrayLength(result)); in sminmaxp()
1209 result[(i >> 1) + (j * lanes / 2)] = dst_val; in sminmaxp()
1401 unsigned lanes = LaneCountFromFormat(vform); in uminmaxp() local
1405 for (unsigned i = 0; i < lanes; i += 2) { in uminmaxp()
1414 VIXL_ASSERT(((i >> 1) + (j * lanes / 2)) < ArrayLength(result)); in uminmaxp()
1415 result[(i >> 1) + (j * lanes / 2)] = dst_val; in uminmaxp()
2170 // always has S-lanes or smaller, so signed integer overflow -- undefined
7091 // which occupies the corresponding lanes o
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/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h950 // vrecpe and vrsqrte only support floating point lanes.
1447 // lanes of a Q register is equivalent to loading/storing the high D reg,
1448 // modulo number of lanes in a D reg. This constructor decides, based on the
1454 LoadStoreLaneParams(uint8_t laneidx, NeonSize sz, int lanes) in LoadStoreLaneParams() argument
1455 : low_op(laneidx < lanes), sz(sz), laneidx(laneidx % lanes) {} in LoadStoreLaneParams()
/third_party/skia/third_party/externals/swiftshader/src/Pipeline/
H A DSpirvShaderDebugger.cpp262 // Search each of the lanes for the named variable.
1062 uint8_t *base; // Common base address for all SIMD lanes.
1342 PerLaneVariables lanes;
2147 // Don't trap if no lanes are active.
2149 // lanes, but this is complicated due to ensuring that all reactor
2173 auto laneLocals = std::make_shared<vk::dbg::Struct>("Lane", globals.lanes[lane]);
2388 locals[lane]->extend(globals.lanes[lane]);
2406 globals.lanes[lane]->put(name, makeDbgValue(simd[lane]));
2444 globals.lanes[lane] = vc;
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_pipeline_rt.c1397 unsigned lanes = device->physical_device->rt_wave_size; in build_traversal_shader() local
1398 unsigned elements = lanes * MAX_STACK_ENTRY_COUNT; in build_traversal_shader()
1404 nir_ssa_def *stack_idx_stride = nir_imm_int(&b, lanes); in build_traversal_shader()
/third_party/ffmpeg/libavcodec/x86/
H A Dcelt_pvq_search.asm129 VPBROADCASTD m2, xm2 ; m2=i (all lanes get same values, we add the offset-per-lane, later)
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-logic-arm64.cc1127 int lanes = LaneCountFromFormat(vform); in SMinMaxP() local
1131 for (int i = 0; i < lanes; i += 2) { in SMinMaxP()
1140 DCHECK_LT((i >> 1) + (j * lanes / 2), kMaxLanesPerVector); in SMinMaxP()
1141 result[(i >> 1) + (j * lanes / 2)] = dst_val; in SMinMaxP()
1277 int lanes = LaneCountFromFormat(vform); in UMinMaxP() local
1290 DCHECK_LT((i >> 1) + (j * lanes / 2), kMaxLanesPerVector); in UMinMaxP()
1291 result[(i >> 1) + (j * lanes / 2)] = dst_val; in UMinMaxP()
/third_party/node/deps/v8/src/compiler/backend/ia32/
H A Dcode-generator-ia32.cc2344 // Positive overflow lanes -> 0x7FFFFFFF in AssembleArchInstruction()
2345 // Negative lanes -> 0 in AssembleArchInstruction()
2353 // convert. Overflow lanes above max_signed will be 0x80000000 in AssembleArchInstruction()
2355 // Add (src-max_signed) for overflow lanes. in AssembleArchInstruction()
2372 // Positive overflow lanes -> 0x7FFFFFFF in AssembleArchInstruction()
2373 // Negative lanes -> 0 in AssembleArchInstruction()
2380 // convert. Overflow lanes above max_signed will be 0x80000000 in AssembleArchInstruction()
2382 // Add (src-max_signed) for overflow lanes. in AssembleArchInstruction()
3053 uint32_t lanes = i.InputUint32(j); in AssembleArchInstruction() local
3056 uint8_t lane = lanes >> in AssembleArchInstruction()
3065 uint32_t lanes = i.InputUint32(j); AssembleArchInstruction() local
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/third_party/node/deps/v8/src/execution/mips64/
H A Dsimulator-mips64.cc6698 #define BZ_DF(witdh, lanes) \
6703 for (i = 0; i < lanes; ++i) { \
6708 BranchHelper_MSA(i != lanes); \
6728 #define BNZ_DF(witdh, lanes) \
6733 for (i = 0; i < lanes; ++i) { \
6738 BranchHelper_MSA(i == lanes); \
/third_party/node/deps/v8/src/execution/mips/
H A Dsimulator-mips.cc6397 #define BZ_DF(witdh, lanes) \
6402 for (i = 0; i < lanes; ++i) { \
6407 BranchHelper_MSA(i != lanes); \
6427 #define BNZ_DF(witdh, lanes) \
6432 for (i = 0; i < lanes; ++i) { \
6437 BranchHelper_MSA(i == lanes); \
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dassembler-riscv64.h1822 LoadStoreLaneParams(uint8_t laneidx, int sz, int lanes) in LoadStoreLaneParams() argument
1823 : sz(sz), laneidx(laneidx % lanes) {} in LoadStoreLaneParams()

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